The leading edge semiconductor logic landscape has in recent years collapsed to just four companies. The following is a summary of what is currently known about each company’s plans and how they compare. ASML has analyzed many logic nodes and developed a formula that normalizes processes to a “standard node”.… Read More
Tag: 10nm
A new world of 10nm design constraints
Every time the industry transitions to a smaller process node IC design software undergoes extensive updates.
I talked to a couple of experts in physical design at Mentor Graphics about what is involved in making place-and-route software ready for a new node. This is what I learned from Sudhakar Jilla, the IC design marketing director… Read More
What is Inside the iPhone 7?
TSMC is the bellwether for not only the foundry business, since they are the dominant player, but also the semiconductor industry as a whole. You could also argue that TSMC is a sneak peek into the world economy since they build capacity based on their customer’s forecasts and the world now revolves around semiconductors.
The other… Read More
SEMICON West – Leti FDSOI and IOT, status and roadmap
On Tuesday, July 12th at SEMICON West I had an opportunity to sit down with Marie Semeria, the CEO of Leti and discuss the status and future of FDSOI. Leti pioneered FDSOI 15 years ago and has been the leading FDSOI research ever since.
Two years ago Leti and ST Micro demonstrated products on 28nm that are cost competitive with bulk technology.… Read More
IMEC Technology Forum at SEMICON – Coventor could save you billions!
The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.… Read More
IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium
At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview… Read More
SEMICON West 2016 Preview
Next week is SEMICON West and I plan to be there all week. SEMICON West is a great opportunity to see the latest in equipment and materials on the show floor, to attend all the talks and receptions and to meet with various industry experts.… Read More
IMEC Technology Forum (ITF) – Secrets of Semiconductor Scaling
IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.… Read More
IMEC Technology Forum (ITF) – Moving the Electronics Industry Forward
IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.
Gary Patton is the Chief Technical Officer and Senior… Read More
IMEC Technology Forum (ITF) – EUV When, Not If
For me personally EUV has been something of a roller coaster ride over the last several years. I started out a strong believer in EUV but then at the SPIE Advanced Lithography Conference in 2014 TSMC gave a very negative assessment of EUV, and there was a SEMATECH paper on high NA EUV that struck me as extremely unlikely to succeed. I … Read More