Moore’s Law is dead, long live Moore’s Law – part 2

In the first installment of this series on Moore’s law we examined what Moore’s law is and presented some data on how it has affected the industry. In this installment we will discuss the manufacturing cost reduction strategies that have made Moore’s law possible.

Manufacturing Cost Drivers
The manufacturing cost of a semiconductor is made up of wafer fabrication, wafer sort, packaging and class test.

Packaging has seen a move from expensive ceramic packages to plastic packages, packaging has moved offshore to low labor cost locations, new smaller and lower cost packages have been introduced such as QFNs and recently gold wire bonding wore has been replaced with copper wire bonds.

For wafer sort and class test, probably the biggest cost reduction has been the move to parallel test where up to hundreds of parts are now tested at the same time.

The single biggest drive of semiconductor cost reductions has been the cost of wafer fabrication where four major factors have driven down cost.

Wafer fabrication cost

Wafer size
The first big driver of wafer fabrication cost reductions has been wafer size transitions. In 1960 wafer sizes were split between 0.75 and 1.0 inch diameter wafers with 0.75” ramping down and 1.0” ramping up. Over the subsequent decades wafer sizes have transitioned all the way to 300mm (~12”) with 450mm (~18” in development). Table 1. Illustrates wafer size transitions.

[TABLE] align=”center” border=”1″
|-
| style=”width: 109px” | Wafer size
| style=”width: 126px” | Year introduced to production
| style=”width: 114px” | Wafer area (cm2)
| style=”width: 101px” | Wafer area increase
| style=”width: 101px” | Years since last new wafer size.
|-
| style=”width: 109px” | 1.5”
| style=”width: 126px” | 1963
| style=”width: 114px” | 11.4
| style=”width: 101px” | 1.44
| style=”width: 101px” | NA
|-
| style=”width: 109px” | 2.0”
| style=”width: 126px” | 1966
| style=”width: 114px” | 20.3
| style=”width: 101px” | 1.78
| style=”width: 101px” | 3
|-
| style=”width: 109px” | 3.0”
| style=”width: 126px” | 1970
| style=”width: 114px” | 45.6
| style=”width: 101px” | 2.25
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 100mm
| style=”width: 126px” | 1974
| style=”width: 114px” | 78.5
| style=”width: 101px” | 1.72
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 125mm
| style=”width: 126px” | 1981
| style=”width: 114px” | 123
| style=”width: 101px” | 1.56
| style=”width: 101px” | 7
|-
| style=”width: 109px” | 150mm
| style=”width: 126px” | 1984
| style=”width: 114px” | 177
| style=”width: 101px” | 1.44
| style=”width: 101px” | 3
|-
| style=”width: 109px” | 200mm
| style=”width: 126px” | 1988
| style=”width: 114px” | 314
| style=”width: 101px” | 1.78
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 300mm
| style=”width: 126px” | 1998
| style=”width: 114px” | 707
| style=”width: 101px” | 2.25
| style=”width: 101px” | 10
|-
| style=”width: 109px” | 450mm
| style=”width: 126px” | 2022
| style=”width: 114px” | 1,590
| style=”width: 101px” | 2.25
| style=”width: 101px” | 24
|-

Wafer size transitions require new larger more expensive equipment increasing depreciation, facility and maintenance costs. Consumable usage increases and wafers get more expensive. Indirect labor per wafer typically stays relatively flat and direct labor per wafer has actually gone down due to increasing automation. The net result is that the cost per unit area of processed wafer typically goes down, for example table 2 presents a comparison of 300mm costs versus 200mm costs for an identical logic process.

[TABLE] align=”center” border=”1″
|-
| style=”width: 139px” | Wafer size
| style=”width: 192px” | $/wafer
| style=”width: 150px” | $/cm2
|-
| style=”width: 139px” | 200mm
| style=”width: 192px” | $1,203.17
| style=”width: 150px” | $3.83
|-
| style=”width: 139px” | 300mm
| style=”width: 192px” | $1,936.11
| style=”width: 150px” | $2.74
|-

The key assumptions are:

• Material: $/cm[SUP]2[/SUP] the same for both sizes (currently approximately true although not at the introduction of a new wafer size).
• Direct Labor (DL) and Indirect Labor (IDL) productivity equal (300mm is actually better for DL).
• Equipment cost: 1.25x (assumes no technology improvements).
• Throughput: 0.52 expose, 0.62 implant and metrology, 1.0x others. Assumes no throughput enhancements that would increase the equipment price.
• Footprint: actual change.
• Maintenance factor: same for both.
• Consumables and utilities: 2.25x (actually has generally been less than this).

The net result is a 28% reduction in cost per unit area. The problem is that as we can see from table 1. the time between wafer size transitions has lengthened dramatically from 3 to 4 years in the past to 10 years for 200mm to 300mm and over 20 years to get from 300mm to 450mm. the net result is that wafer size transitions are no longer a significant contributor to yearly reductions in wafer cost.

Yield
In the early days of the semiconductor industry yields were low and improved slowly. In recent years mature yields are typically in the ninety percentage plus range and the time to achieve mature yields has compressed to around six months. There are of course exceptions; there were reports of yield problems for TSMC at 130nm. At 28nm yield struggles at most foundries gave TSMC a clear early lead and Intel has had well publicized yield issues at 14nm.

The bottom line is that modern yields are so high and time to yield is so fast that further improvement in costs due to faster yield improvement aren’t really possible and yield improvement is no longer a driver of year to year cost improvement.

OEE
In 1995 Sematech introduce OEE to the industry. OEE is basically the percentage of the capacity of a tool that is actually achieved. OEE which stands for Overall Equipment Effectiveness accounts for down time both scheduled and unscheduled, idle time due to no work or no operator, yield loss, speed (tool running slower than normal), set up, qualification lots and engineering wafers. It is basically how many good sellable wafers a tool produces per hour divided by the tool capacity in wafers per hour.

When Sematech went out and surveyed the industry in 1995 they found the industry wide OEE was only averaging 30%. A major program to improve OEE was then undertaken and by 2003 a new Sematech study found OEE had improved to 40%.

Generally speaking OEE follows these principles:

• OEE is better for newer equipment designed to produce smaller linewidths because of the work the equipment manufacturers continue to put into improving equipment performance.
• OEE is lower for high mix fabs due set up time for change overs and qualification runs and higher for low mix fabs.
• OEE is better for larger fabs due to the ability to better match equipment capacity.

In general from lower to higher OEE we can rank fabs as follow: high mix logic fabs (foundry), low mix logic, single process large DRAM fabs, single process massive NAND fabs.

OEE today ranges from around 50% to over 70%. It should be noted here that due to cycle time reasons it is not desirable to drive OEE to 100% and some of the largest NAND fabs are approaching the “optimal OEE”. OEE is therefore becoming less of a year to year cost reduction driver.

Linewidth shrinks
The largest and most consistent driver of cost reductions has been linewidth shrinks. Linewidth shrinks have historically increased wafer cost but provided a larger increase in transistors per unit area and therefore reduced cost per transistor.

In 1974 Dennard, et.al. of IBM disclosed the concept of MOSFET scaling. Basically you take an existing linewidth, for example 250nm and you multiply it by a scaling factor resulting in a linewidth of 180nm. By shrinking from 250nm to 180nm you increase the transistors per unit area and the transistor performance simultaneously as long as you scale everything correctly. Table 3 summarizes constant electric field scaling from 250nm to 180nm.

[TABLE] align=”center” border=”1″
|-
| rowspan=”2″ style=”width: 162px” | Parameter
| rowspan=”2″ style=”width: 60px” | Scaling factor
| colspan=”3″ style=”width: 342px” | Devices
|-
| style=”width: 108px” | Before
| style=”width: 114px” | Calculation
| style=”width: 120px” | After
|-
| style=”width: 162px” | Gate length (Lg)
| style=”width: 60px” | 1/k
| style=”width: 108px” | 250nm
| style=”width: 114px” | 250/1.4
| style=”width: 120px” | 180nm
|-
| style=”width: 162px” | Operating voltage
| style=”width: 60px” | 1/k
| style=”width: 108px” | 1.8 volts
| style=”width: 114px” | 1.8/1.4
| style=”width: 120px” | 1.3 volts
|-
| style=”width: 162px” | Packaging density
| style=”width: 60px” | K[SUP]2[/SUP]
| style=”width: 108px” | 1x
| style=”width: 114px” | 1.4[SUP]2[/SUP]
| style=”width: 120px” | 2x
|-
| style=”width: 162px” | Power consumption
| style=”width: 60px” | 1/k[SUP]2[/SUP]
| style=”width: 108px” | 1x
| style=”width: 114px” | 1/1.4[SUP]2[/SUP]
| style=”width: 120px” | 0.5x
|-
| style=”width: 162px” | DC power density
| style=”width: 60px” | 1
| style=”width: 108px” | 1
| style=”width: 114px” | NA
| style=”width: 120px” | 1
|-
| style=”width: 162px” | Circuit delay
| style=”width: 60px” | 1/k
| style=”width: 108px” | 1
| style=”width: 114px” | 1/1.4
| style=”width: 120px” | 0.7
|-
| style=”width: 162px” | Power delay product
| style=”width: 60px” | 1/k[SUP]3[/SUP]
| style=”width: 108px” | 1
| style=”width: 114px” | 1/1.4[SUP]3[/SUP]
| style=”width: 120px” | 0.4
|-
| style=”width: 162px” | Functional throughput
| style=”width: 60px” | K[SUP]3[/SUP]
| style=”width: 108px” | 1
| style=”width: 114px” | 1.4[SUP]3[/SUP]
| style=”width: 120px” | 2.7
|-

From table 3. we can see that packing density (transistors per unit area increased by 2x, power consumption was cut in half, circuit delay was decreased by 30% and functional throughput went up by 2.7x.

In order to accomplish constant electric field scaling gate oxide thickness also has to scale to maintain good electrostatic control over the gate. Unfortunately at the 90nm logic node gate oxides became so thin that further reductions in thickness resulted in too much leakage. This will be discussed further in the section on logic devices but basically mobility enhancement through strain was used until high-k gate oxide was introduced.

Figure 1. illustrates the linewidths for the market leaders in four main segments. Plotted on figure 1 are Intel MPU and TSMC SOC minimum metal pitches, Samsung DRAM bit line pitch and Samsung NAND polysilicon pitch.

Figure 1. Linewidth trends for Samsung DRAM, TSMC SOC, Intel MPU and Samsung NAND. Source, IC Knowledge.

As you can see from figure 1. all four segments have continued to scale down linewidths. The problem is that as pitch drops below approximately 80 nanometers single patterning with immersion scanners can no longer print the required patterns and multipatterning is required.

Multipatterning
There are two main approaches to multipatterning:

Litho-etch splits patterns up into multiple masks where a mask is applied and etched into the wafer and then additional masks and etches are performed. Table 4. Summarizes various litho-etch techniques.

[TABLE] align=”center” border=”1″
|-
| style=”width: 127px” | Technique
| style=”width: 127px” | Abbreviation
| style=”width: 127px” | Pitch
| style=”width: 127px” | Masks
|-
| style=”width: 127px” | Litho-etch – Litho-etch
| style=”width: 127px” | LE2
| style=”width: 127px” | ~60nm
| style=”width: 127px” | 2
|-
| style=”width: 127px” | Litho-etch – Litho-etch – Litho-etch
| style=”width: 127px” | LE3
| style=”width: 127px” | ~50nm
| style=”width: 127px” | 3
|-
| style=”width: 127px” | Litho-etch – Litho-etch – Litho-etch – Litho-etch
| style=”width: 127px” | LE4
| style=”width: 127px” | ~40nm
| style=”width: 127px” | 4
|-

The second technique is Self-Aligned Multipatterning. The self-aligned techniques can double, quadruple or octuple the pitch but they create ovals around a mandrel and require cut masks to create lines. Depending on the required pitch, large number of cut masks may be required. Self-aligned multipatterning is also primarily useful for line-space pairs and not as useful for 2D patterns. Table 5. Summarizes self-aligned multipatterning.

[TABLE] align=”center” border=”1″
|-
| style=”width: 127px” | Technique
| style=”width: 127px” | Abbreviation
| style=”width: 127px” | Pitch
| style=”width: 127px” | Masks
|-
| style=”width: 127px” | Self-Aligned Double Patterning
| style=”width: 127px” | SADP
| style=”width: 127px” | 40nm
| style=”width: 127px” | 3 for 40nm
|-
| style=”width: 127px” | Self-Aligned Quadruple Patterning
| style=”width: 127px” | SAQP
| style=”width: 127px” | 20nm
| style=”width: 127px” | 6 for 20nm
|-
| style=”width: 127px” | Self-Aligned Octuple Patterning
| style=”width: 127px” | SAOP
| style=”width: 127px” | 10nm
| style=”width: 127px” | 10 for 10nm
|-

As we can see from tables 4 and 5 multipattering enables much smaller pitches than the 80nm single exposure limit but at the cost of more masks and other additional patterning. There are also edge placement concerns issues that may limit the ability to achieve some of the smallest pitches.

The bottom line of all this is that as we move further into the era of multipatterning cost per wafer is going up faster than it has historically increased slowing the rate of cost reduction. As we will see in the next three installments there are also structural issues that will ultimately stop our ability to continue to scale at all.

In the next three installments we will examine the specific issues and status of DRAM, Logic and NAND.

Also read:
Moore’s Law is dead, long live Moore’s Law – part 1
Moore’s Law is dead, long live Moore’s Law – part 3
Moore’s Law is dead, long live Moore’s Law – part 4
Moore’s Law is dead, long live Moore’s Law – part 5