VLSIT Conference – imec on CFETs

The 2018 VLSI Technology conference was held in Hawaii in June and is one of the premier conferences covering integrated circuit process technology and circuit design. The Complementary FET (CFET) is an emerging option to continue logic scaling into the next decade. At the conference imec, GLOBALFOUNDRIES, Tokyo Electron and Coventor presented “The Complementary FET (CFET) for CMOS scaling beyond N3,”. I have copies of the paper and presentation and had the opportunity to interview one of the authors, Julian Ryckart of imec.

The mainstream technology of choice for high performance ICs is currently the FinFET. Leading foundries are ramping 7nm FinFET technologies with risk starts of 5nm FinFETs planned for next year. Looking forward, somewhere around 3nm a transition is expected to horizontal nanowire/nanosheet (HNW/HNS) technologies, in fact Samsung has already announced a 3nm “Gate All Around” technology based on nanosheets for 2021. As we look even further forward beyond the introduction of HNS, a variety of scaling issues present themselves. The CFET is an emerging concept to provide scaling by stacking devices in the third dimensions.

In CMOS technologies nFETs and pFETs are used in pairs so that when the nFET is on, the pFET is off or vice versa. This results in low power consumption because current only flows during switching. nFET and pFET pairs are therefore a natural primitive in CMOS logic. In current technologies the nFET and pFET devices are fabricated in the same plane, in a CFET technology the nFET and pFET devices are stacked on top of each other providing an area reduction for the same pitches. The combination of the CFET with buried power rails can reduce the track height of the cells as well and for SRAMs a 40% structural gain is seen for the same pitches. Figure 1 illustrates some of the scaling advantages of CFETs.

The CFET fabricated in this work is a fin over fin configuration with pFET fin on the bottom to benefit from substrate induced stress and the nFET vertical sheet on the top. Due to lower hole mobility in silicon, pFETs are typically weaker devices than nFETs and need extra stress to match the nFET performance. Putting the nFET on top also makes fabrication easier because the nFET work function is a sub-set of the pFET work function.

This CFET process features separate electrodes for the nFET and pFET allowing connections to be made either up to the interconnect stack or down to the buried power rails. Figure 2 illustrates the split electrode and the buried power rail.

The split gate CFET process makes routing easier and the routing propagates up into place and route. The ability to shift P and N connections “north and south” means that only 1D connections are needed.

The stacked devices produced by this process are comparable to conventionally fabricated FinFETs in terms of performance. Parasitics can makes one of the devices different from the other and needs to be addressed and mitigated. There are some advantages to this process that can even result in better than FinFET performance. The CFET drain extensions can be minimized reducing gate to drain parasitic capacitance and improving performance, see figure 3.

In a standard FinFET the middle of line is routed parallel to the gate whereas for a CFET it is orthogonal to the gate also reducing gate to drain capacitance.

The process of building CFETs shares many steps with standard FinFET processes. A CFET process doesn’t add very many steps but the steps are more critical and require better control. Fill – planarize – etch-back steps in the CFET process require precise depth control of the etch back in order to fabricate and connect to the stacked devices.

Currently CFET devices are a single threshold voltage and it is already hard to build the sperate nFET and pFET work functions. Supporting multiple threshold voltages is an unsolved problem and appears very complicated. This is however unlikely to be a show stopper for CFETs because there aren’t any sliver bullets any more and CFETs appear to be the most general-purpose solution available.

I asked Julian about stacking beyond 2 layers, I am aware of groups exploring stacking up to 7 layers and more as a long-term scaling path that could even relax pitch requirements. Julian’s belief is that 2 layers makes sense because it creates a natural primitive of CMOS, but he was difficulty seeing scaling beyond 2 layers.

Some simple cost comparisons show that CFETs provide scaling less expensively than shrinking pitches by lithography.

In summary CFETs offer an intriguing option for scaling beyond HNW/HNS processes.

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