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Intel – “Super” Moore’s Law Time warp-“TSMC inside” GPU & Global Flounders IPO

Intel – “Super” Moore’s Law Time warp-“TSMC inside” GPU & Global Flounders IPO
by Robert Maire on 10-31-2021 at 6:00 am

“Super” Moore’s Law- 5 nodes in 4 years- Too good to be true?
Gelsinger said “Intel will be advantaged with High NA EUV”
Ponte Vecchio better with “TSMC Inside”
Global Flounders IPO as price drops on public debut

Lets do the time warp again….(apologies to Riff Raff)

Its just a jump to the left
And then a step to the right….

Pat Gelsinger is talking about Intel’s ability to bend time (and Moore’s Law) to Intel’s will and go through 4 nodes in 5 years. This translates to a 1.25 year per node cadence versus the original Moore’s Law 2 years and recent Intel 3 to 4 or more years per node. Even TSMC can’t do that as its yearly advances are less than a full node and usually more of an incremental tuning.

Whats more interesting is that Pat seems dead serious about what he coined as “Super Moore’s Law“. We didn’t hear much hedging in the statements. He is dead serious.

This is going to be very binary as it will either be the world’s greatest success and comeback or it will prove very embarrassing.

Gelsinger: “we’re going to be advantaged at High NA (EUV)”

We have previously pointed out that Intel is at a huge disadvantage in EUV tool count versus TSMC and even Samsung. We also suggested that Intel likely cut some sort of understanding with ASML to be the first large supporter of High NA much as TSMC was the first out of the gate with EUV.

What we don’t see is how Intel will have an advantage. Its not like ASML will sell its High NA tools only to Intel and forsake its biggest and bestest customer TSMC. Thats not gonna happen.

Intel has also not gone through all the pain and learning process of EUV and has a miniscule amount of experience in real world use as compared to TSMC years of experience running many, many wafers. on EUV tools.

Much of the EUV learning that Intel has yet to do is a prerequisite for figuring out High NA.

Its quite clear that with all the experience gained in its huge lead in EUV that TSMC will enter High NA EUV with an advantage over Intel and not the other way around.

This suggests that “Ribbon” transistors are the main advantage that Intel can bring to bear and we just don’t see it.

Backside power has been around for a while and is not unique to Intel.

So we still want to understand how Intel goes from 3-4 years per Moore’s Law node to 1.25 years per node virtually overnight (not counting the fact that High NA is years away)

With a bit of a mind flip
You’re into the time slip

Intel’s Ponte Vecchio better than expected with “TSMC Inside”

It appears the performance of Ponte Vecchio is better than originally planned. Could it be that using some TSMC silicon inside made the difference?
TSMC’s N5 process seems to be quietly helping boost performance that Intel’s 7NM couldn’t deliver.

We think that Intel’s use of TSMC silicon and “tiles” will be much higher than anticipated as Intel needs the performance of TSMC’s silicon process to be competitive versus others in the space.

We find it mildly hypocritical that while Intel management bashes global dependence on TSMC it is on a path to increase just that.

Global Flounders in its IPO debut.

Global Foundries priced its stock offering at $47 only to have it drop on its first trading day. At one point it was down to almost $44 before closing in the after market at $46 (even after some end of day trading “support”) Not a very auspicious start as most IPO’s tend to “pop” on the first day of trading. Perhaps investors were expecting something different from a company that can’t make money in the strongest industry conditions.

At roughly 5 times trailing revenue, GloFo is valued similarly to a foundry company that actually makes money at similar revenue levels. SMIC in China….which is likely a better stock buy if you want a trailing, smaller, foundry.

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