Chiplets at the Design Automation Conference with OpenFive

SemiWiki has been tracking the popularity of chiplets for two years now so it was not surprising to see that they played a key role at DAC. The other trend we foresaw was that the ASIC companies would be early chiplet adopters and that has proven true. One of the more vocal proponents of chiplets at DAC#59 was OpenFive, a 17+ year spec-to-silicon design company with more than 350 tapeouts and more than 150M parts shipped, simply amazing!

Chiplets are all about reusability and quick time-to-market for chips big and small. Using silicon proven hard IP enables design starts by reducing costs and cutting tapeout time, which of course plays perfectly into the spec-to-design ASIC business perfectly.

OpenFive has gained significant momentum in this trending market with several early customer engagements and multiple wins on D2D IP for chiplets. OpenFive also recently announced that they have joined the Universal Chiplet Interconnect Express (UCIe) Consortium which we covered (OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium). OpenFive is very well positioned based on their D2D IP, custom silicon implementation, and advanced packaging and manufacturing experience.

We have also written about IP Subsystems and Chiplets for Edge and AI Accelerators and Die-to-Die Interface PHY and Controller Subsystem for Next Generation Chiplets.

In April OpenFive launched a die-die interface solution for the Chiplet Ecosystem:

• Features IOs running at up to 16Gbps (effective throughput of ~1.75Tbps/mm)
• Features extremely low latency and <0.5pJ/bit offering best power performance benchmarks

It’s all about the ecosystem, right?

The new D2D PHY helps disaggregate large SoC die into smaller die, resulting in better yield, cost and power savings. It features up to 16Gbps NRZ signals with clock forwarding architecture. Each channel, comprising of 40 IOs, can provide effective throughput of up to ~1.75Tbps/mm. Users can stack up multiple channels to further increase overall throughput. The PHY also features built-in PLL, programmable output drivers, and link training state machines.

“The D2D subsystem, including both the controller and PHY, provides best-in-class latency, performance and power profile for various IO, CPU and analog chiplets,” said Ketan Mehta, Sr. Director, Product/Application Marketing, SoC IP, at OpenFive.

“OpenFive’s die-to-die connectivity IP solution will enable widespread integration of proven solutions from chiplet ecosystem partners,” said Mohit Gupta, SVP and GM, SoC IP at OpenFive. “As a custom ASIC and IP provider, OpenFive is well-positioned to provide an entire chiplet solution to our customers at any stage of development, whether it be during design, integration, manufacturing, or testing of Known-Good-Die (KGD).”

In their DAC booth OpenFive also highlighted an eye catching demo of an AI vision application and working silicon SoC boards which included:

• HBM2E, D2D I/O, and RISC-V on 5nm SoC
• LPDDR5/4X brought up on 7/6nm SoC
• HBM2E I/O and RISC-V on 5nm SoC
• HBM2E on 7nm SoC

For more information, please visit www.openfive.com/ip

About OpenFive
OpenFive, a SiFive business unit, is focused on custom silicon solutions and differentiated IP. With spec-to-silicon design capabilities, customizable SoC platforms, and differentiated IP for Artificial Intelligence, Cloud/Datacenter, High Performance Computing, Networking, and Storage applications, OpenFive is uniquely positioned to deliver highly competitive processor agnostic domain-specific SoCs.

The OpenFive IP portfolio includes High-Bandwidth Memory (HBM3/2E) and low power LPDDR5/4x memory subsystems; Die-to-Die (D2D) interface IP subsystems for heterogeneous multi-die connectivity including chiplets; low-latency, high-throughput Interlaken interface IP for chip-to-chip connectivity; 400/800G Ethernet MAC/PCS subsystems, and USB controller IP. OpenFive offers end-to-end expertise in custom SoC architecture, design implementation, software, silicon validation, and manufacturing to deliver high-quality silicon in advanced nodes down to 4nm.

Also read:

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads

Die-to-Die Interface PHY and Controller Subsystem for Next Generation Chiplets

Enabling Edge AI Vision with RISC-V and a Silicon Platform