The world is moving towards domain-specific architectures. Working collaboratively with our partners and customers, OpenFive is innovating with segment-specific silicon solutions based on optimized processor and SoC IP.
OpenFive, the leading provider of customizable, silicon-focused solutions with differentiated IP, today announced the launch of a new Die-to-Die (D2D) interface IP portfolio to serve next-generation chiplet based designs for Networking, HPC, and AI Markets.With recent advances in package technologies and the cost per area increase in newer nodes, it is advantageous to connect multiple dies, or chiplets, on a single package with silicon-based interposer or an organic substrate.
When standard products don’t meet your business or technical
requirements, it’s time to go custom. Specialized custom SoC
solutions can be optimized for power, performance, and area,
giving you greater design flexibility and a competitive edge.
OpenFive’s Idea-to-Silicon capabilities combined with our advanced design methodologies on leading-edge 5nm, 7nm and 12nm foundry processes, and 2.5D packaging technology enable exciting new designs applications such as Artificial Intelligence (AI), Edge computing, Networking, and High-Performance Computing (HPC).
Flexible Engagement Models
Benefits of using an Idea-to-Silicon Methodology
Ongoing product development costs on derivatives of existing chip designs are high and make it hard to integrate new IP. The OpenFive Idea-to-Silicon methodology reduces cost and time to market to enable your silicon with your preferred software stack.
The OpenFive Idea-to-Silicon methodology enables optimized layout for power, performance, and size requirements, and reduces time to market for ongoing product roadmap development.
OpenFive’s Idea-to-Silicon methodology provides an ideal starting point to explore and enter into key markets with the advantage of a faster design cycle by integrating required IPs from our wide IP portfolio, thereby providing a competitive advantage.
Front-end Design, Integration, and Verification
Design expertise for building scalable, customized SoCs with in-house design, integration, and advanced verification using automated tools and methodology.
- SOC Micro-architecture
- RTL Design and Synthesis
- SOC IP Integration
- Design Verification
- FPGA Prototyping
OpenFive experts in Physical Design Methodologies have completed complex chip tape-outs in a variety of process nodes including 7nm. These designs include complex high speed interfaces such as HBM2E, PCIe Gen4, and 56G SerDes targeting high-performance applications in AI, Networking, and High-Performance Computing (HPC)
We partner with world-class foundries and offer wide range of processes including leading edge 5nm, 7nm, 12nm, 16nm for high performance logic, and more mature nodes for analog or mixed signal applications.
OpenFive is a long-standing member of TSMC’s Value Chain Aggregator (VCA) program.
Package and assembly
OpenFive provides a complete solution from package selection through design and development, to high-volume manufacturing. We understand the importance of selecting the proper packaging solution to meet the technical and cost constraints of each design. Our packaging capabilities include 2.5D technology, and OpenFive’s extensive experience enables us to meet the unique needs of each customer and successfully launch their product.
2.5D IC is a packaging technology where multiple die are placed face down and side by side on a silicon or organic interposer. The active surface of the die has micro-bumps that connect to pads on the surface of the silicon interposer. Connections from these pads directly connect to TSVs (Through Silicon Vias), which pass through the interposer substrate and connect to the package substrate. The connections from the pads can also be connected through interposer routing to other TSVs that are in-turn connected to pads and micro-bumps of other die on the interposer. 2.5D IC technology helps reduce interconnection length between multiple dies assembled on the interposer, leading to lower power consumption and lower latency as well as an increase in the number of interconnection routes on the interposer, which results in increased bandwidth compared to traditional 2D off-chip interconnections.
The picture above shows mounting 2 or more silicon dies onto an interposer die and then assembling the whole system into a single package.
Silicon based on 2.5D technology is making inroads into high performance computing, graphic processors, and AI (Artificial Intelligence) processors utilizing High Bandwidth Memories (HBM). These HBMs are available as tested KGDs (Known Good Die), and are mounted on the interposer along with die containing the main processor and HBM controller. High density routing through the interposer interconnects the two die.
The main advantages of this technology are miniaturization, enhanced performance, lower latency, increased bandwidth and power efficiency. Key advantage of 2.5D technology is that the die that are mounted on interposer need not utilize the same process node or technology. This helps in using die manufactured in various technology nodes. As an example, a HBM 3D stacked memory die can be mounted on the interposer with a processor die manufactured in 7nm process technology.
Share your vision with our dedicated sales team and we’ll shape a custom silicon solution that fits your needs.
ASIC Design Specs
If you already have a design spec in mind, our team can help you with the budgetary pricing and schedule.