OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium

Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between chiplets within a package. The objective is to enable an open chiplet ecosystem. Although the initial specification for UCIe was developed by Intel, a consortium was announced in March with Intel, AMD, Arm, Google, Meta, Microsoft, ASE Group, Qualcomm, Samsung and TSMC as its promoting members. The promoting members represent a diverse functional cross section of semiconductor ecosystem expertise. Just in the three months since the consortium’s formation, many companies have joined as contributing level members (see Figure below).

That is a lot of committed members keen on progressing this universal interface standard. Each of these members brings its unique expertise to the consortium and of course expect their involvement to further their own business goals as well as the industry’s progress. OpenFive announced their membership recently and this post will look at what that means for them as well as for the consortium and the industry. The post will review OpenFive’s history and track record, its UCIe membership, and its pending acquisition by Alphawave. In essence, its Past, Present and Future.

Past

The OpenFive team has been delivering custom silicon for over 15 years. The key to increased productivity is leveraging pre-verified IP subsystems and OpenFive has built many such IP subsystems to support its customer base. These IP subsystems address connectivity and memory interfaces. You can learn more at their IP portfolio page.

As chiplets-based development started picking momentum a few years ago, OpenFive started playing an instrumental role to support this movement. OpenFive developed a die-to-die (D2D) IP subsystem. The subsystem supports low-power, high-throughput, and low-latency links enabling quicker integration for heterogenous chipset connections in wired communications, AI and HPC applications. It introduced the industry’s first Die-to-Die (D2D) Controllers which are agnostic to physical link interfaces, thereby supporting OHBI and BoW interfaces for chiplets. You can learn more from a SemiWiki post published last year.

Present

The current industry trend for scalable silicon architectures makes efficient and standardized Die-to-Die and Chip-to-Chip interconnects critical for SoC solutions. This has created a need for strong experience in advanced packaging, test, and production in leading-edge process nodes such as 5nm as well as older nodes. OpenFive is staying ahead by investing in die-to-die (D2D) interfaces, chiplet technology and 2.5D packaging. They can support chiplets that enable partitioning of the design into different functions, and the option to choose a process optimized for that particular function.

With their capabilities to engage in a spec-handoff, netlist handoff or production handoff, OpenFive can service their customers, whether a chiplet interface standard exists or not. But a standard such as the UCIe interface certainly makes it easier, faster and consistent and is expected to accelerate the growth of chiplet based products market.

The addition of support for UCIe support is a natural progression to their existing support for OHBI and BoW interfaces. As a contributing level member of the UCIe consortium, OpenFive will actively participate in the Electrical and Protocol subgroups. They get to drive the specification and influence the direction of the technology. And, of course access the intermediate (dot level) specifications. OpenFive will leverage its depth of experience from multiple customer engagements and its silicon platforms.

Future

In March of 2022, Alphawave IP Group announced a definitive agreement to acquire OpenFive. The transaction is expected to close in the second half of 2022. As per that press announcement, the acquisition will enhance Alphawave’s chiplet design capabilities. The combined company will offer an expanded die-to-die connectivity portfolio that will accelerate chiplet delivery capabilities to customers. The acquisition will nearly double the number of connectivity-focused IPs available to customers. Post-acquisition, the company will become a one-stop-shop for customers bundled connectivity needs in the most advanced technologies at 5nm, 4nm, 3nm and beyond.

Customers looking to implement their chiplet-based SoCs for Cloud/Datacenter, AI/HPC, and Networking applications can expect to benefit by leveraging OpenFive’s leading-edge custom silicon implementation and advanced 2.5D packaging capabilities together with their highly optimized memory and connectivity IP subsystems.

Also read:

IP Subsystems and Chiplets for Edge and AI Accelerators

A 2021 Summary of OpenFive

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads