Accellera sponsored a luncheon panel discussion at #60DAC, so I registered and attended to learn more about one of the newest working groups for Clock Domain Crossing (CDC). An overview of Accellera was provided by Lu Dai, then the panel discussion was moderated by Paul McLellan of Cadence, with the following panel members:
Panel Opening Remarks
Anupam Bakshi – has been with Agnisys since 2007, and before that with Gateway Design Automation – where Verilog was invented. Agnisys has been offering CDC automation tools, and is a member of the Accellera working group on CDC standards. He recommended to avoid meta-stability by using a spec-driven and synchronization approach, along with correct by construction design automation. This approach uses declarative attributes, and then engineers simply run the tool.
Frank Schirrmeister – he’s the VP of business development at Arteris, and before that at Cadence. Arteris has a Network On Chip (NOC) focus, and they acquired companies like Semifore to gain system IP, and Magillem to add ISO 26262 and IP-XACT expertise. Frank recommends the generation of registers from a higher-level specification along with CDC logic. As IP for an SoC is provided by multiple vendors, it makes sense to have a CDC standard to ensure that all IP that is integrated will work reliably, so there’s a need for a common intent language.
Dammy Olopade – he’s the working group chair for CDC and a principal engineer at Intel. The new working group was proposed in September 2022, then approved in December, and there are now 96 participants from 22 companies so far. The draft LRM for the CDC is due around December 2023.
Ping Yeung – at Nvidia he is a Senior Manager of Formal Verification. Today bringing up IP blocks with proper CDC checks is very tedious, and too time consuming, so a CDC standard with hierarchy is welcomed. It will allow engineers to focus on CDC at the top level only. They really want to mix internal and external IP blocks easily. Assertions will ensure that models are used correctly, to verify interface properties, constraints and assumptions.
Q&A
Q: Paul – why a CDC standard now?
A: Dammy – at one time all lines of code came from one design team, not now, it’s multiple vendors now. The new model has IP blocks from many different vendors. With so many IP vendors and IP users, a CDC standard is required.
A: Frank – Systemic complexity has grown too large, so a CDC standard is required to keep issues in control. The implementation details now impact the architecture choices. A common language and vocabulary become more important now.
A: Anupam – customers request more CDC validation in their IP integration challenges so we have to act now.
A: Ping – also internal IP blocks must be checked to see if they are being reused properly. What can we do if the original designer is gone?
A: Frank – Since 2000 we’ve been doing abstraction at the same levels, but now we can abstract register generation automatically from a high-level. We now have virtual platforms for HW and SW design.
Q: Paul – what about asynchronous input signals to a chip?
A: Dammy – there has to be a specification for design intentions. What is the spec? How do we design to meet the spec? The first spec should come along in the September time frame. We need to make sure that our clock never glitches, to keep it a synchronous design.
A: Frank – we know how to handle that challenge. We see different clock domains, and then insert the required logic, however the validation bit is a focus of new WG. If your PLLs start to jitter, then video and audio can drift out of synch.
A: Ping – we know how to handle asynchronous signals with known solutions. EDA tools can find CDC domain crossings. When the interfaces have been verified per IP block, how do we capture that verification at the top level, instead of re-verifying all over again?
Q: Paul – how many clock domains are being used today?
A: Anupam – 3-10 is a typical range.
A: Frank – hundreds have been seen. Even the number of re-used IP blocks can be in the hundreds now. Formal verification can be used at full-chip level, but different tools return different results, so some violations are false-positive. IP integrators and IP vendors need to have the same understanding on clock domains.
Q: Paul – what’s next for IP integration after CDC?
A: Ping – Reset domain crossing needs to be standardized.
A: Anupam – what about correct by design approaches? The specification has not been rigorous enough.
A: Frank – integration issues with IP is still a tough issue. What about CDC and safety issues interacting together? Can we ever go beyond RTL abstractions?
A: Anupam – what about FSM and datapath standards? Standards are only at the interfaces for now.
A: Frank – what about MBSE using SysML? Can we get to that level?
A: Dammy – if we already have a working system, then let’s keep working EDA tools then add innovative new tools. Power and performance challenges cannot be easily solved with today’s tools.
Q: Dennis Brophy – what about manufacturing issues and using chiplets?
A: Frank – I asked at UCIe about PHYs working together. Are there any plugfest possibilities? It’s a new layer of complexity.
A: Dammy – there is no interoperable language for CDC now. So we should follow a more correct by construction approach to enable chiplets.
Summary
This panel discussion was fast-paced and the engineers in the audience were actively asking questions and approaching the panelists after the discussion to get their private questions answered. CDC standardization is moving along, and interested engineers are encouraged to join in the working group discussion sessions. If your company is not already an Accellera member, please visit https://accellera.org/about/join for more information on how to join and participate.
Related Blogs
- Accellera Update: CDC, Safety and AMS
- Accellera at DVCon U.S. 2022 in the Metaverse!
- DAC 2021 – Accellera Panel all about Functional Safety Standards
- Accellera Unveils PSS 2.0 – Production Ready
- Functional Safety – What and How
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