Posted on

Self-Aligned Via Process Development for Beyond the 3nm Node

Self-Aligned Via Process Development for Beyond the 3nm Node
by Tom Dillinger on 01-05-2022 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

TEM DoD

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented a research update on their process development activities to realize a “self-aligned via” (SAV) for upcoming nodes, with an interconnect + via flow that provides improved manufacturability.[1]  This article summarizes the highlights of their presentation.

Introduction

The manufacturability of vias needs to address multiple litho, electrical, and reliability measures:

  • tolerance to overlay variation (aka, “edge placement error”, or EPE)
  • consistency of via resistance
  • robustness of via-to-adjacent metal dielectric properties
    • leakage current
    • maximum applied voltage before breakdown (Vbd)
    • dielectric reliability, measured as time-dependent dielectric breakdown (TDDB)

and, of course,

  • exceptional yield

(Note that these issues are most severe for the scaling of lower level metals and vias, denoted as “Mx” in the figures in this article.)

The overlay positioning between a via and an adjacent metal line impacts the dielectric breakdown – both Vbd and TDDB.  The figure below illustrates the overlay versus dielectric breakdown issue of a conventional via, for a representative EPE.

A “self-aligned” via (with a unique dielectric to an adjacent metal line) would provide greater process latitude to address the challenges listed above.

TSMC SAV Process

There are two key steps to the TSMC SAV process flow – the deposition of a “blocking layer” on metal lines and the selective deposition of dielectric-on-dielectric.

  • self-assembled monolayer (SAM) deposition on metal

A unique process chemistry step deposits a monolayer of a blocking material on an exposed metal surface.  This process is based on the affinity of organic chemical chains suspended in a solution to the metal.  The molecular chains are adsorbed on the metal surface, and self-assemble into an organized domain.  As the molecules adsorb over time, they will nucleate into groups and grow until the metal surface is covered with a monolayer.  (The monolayer packs tightly due to the van der Waals forces, the weak net attractive electric force between neutral organic solids.)

This SAM monolayer will serve as a blocking material.  Its composition needs to withstand the thermal exposure of the next step – the selective dielectric deposition on oxide.

  • selective dielectric-on-dielectric (DoD) deposition

Advanced nodes have leveraged atomic layer deposition (ALD) steps for several generations.  A gas phase “pre-cursor” is introduced into the process chamber.  Due to chemisorption, a unique pre-cursor monolayer is deposited on the wafer surface.  The pre-cursor adheres to the surface, but not to itself – no successive pre-cursor layers are deposited.  The chamber is then purged of the excess pre-cursor, and a co-reagent is subsequently introduced.  The chemical reaction results in a final monolayer of the desired reaction product that remains on the surface, while the excess co-reagent and reaction by-products are pumped out.  The cycle can be repeated to deposit multiple “atomic” layers.  ALD has been widely adopted for the deposition of metal and thin-oxide dielectric materials. A key advantage of current ALD processes is they operate uniformly and conformally on the exposed wafer surface.

An active area of research is to provide selective area atomic layer deposition, where the pre-cursor only adheres to a specific material surface.  The goal is the pre-cursor adsorption is suppressed on specific areas – in this case, the SAM molecules on the metal.

TSMC explored a selective deposition chemical process, for dielectric-on-dielectric layer buildup.  The images in the figure below depict the process flow to raise a dielectric layer above the existing surface oxide.

The SAM blocking layer precludes the selective deposition on the exposed dielectric.  As mentioned earlier, the blocking layer must withstand exposure to the elevated temperature of the dielectric-on-dielectric selective deposition.  TSMC indicated that higher DoD process temperatures improve the etch selectivity of the dielectric pedestal to the surrounding low-K inter-level dielectric for the via, to be discussed next.

The image labeled “DoD” in the figure above illustrates the wafer after dielectric-on-dielectric deposition and after removal of the SAM blocking material over the wafer, prior to the addition of the low-K dielectric.

The image on the right shows the final via connection, after low-K dielectric dep/etch and via patterning.  The added DoD material serves as a suitable “etch stop”, due to the lower etch rate compared to the low-K material.  This image illustrates the via-to-adjacent metal dielectric, in the presence of a significant overlay shift.

The figure below illustrates how the added dielectric-on-dielectric layer improves via robustness.  The “control” transmission electron microscopy image (without the DoD) shows excessive via etch of the original dielectric, with little isolation to the adjacent Mx line – not particularly tolerant of overlay error.  The DoD TEM image shows vastly improved isolation.

Experimental Electrical and Reliability Data for the SAV Process

The various figures below show the experimental data from the TSMC SAV process development team.  The Control data reflects the standard via patterning process without the selective DoD layer deposition.

  • via resistance

Both single via and via chain (yield assessment) resistance values show no difference between the control and DoD processes.

  • via-to-adjacent Mx reliability (leakage current, Vbd, TDDB)

To assess the process window, the TSMC team evaluated the leakage current and Vbd with an intentional via-to-Mx overlay shift.  Note that the control process would not support a 4nm overlay tolerance.

To ensure the additional DoD process steps did not adversely impact the characteristics of the existing Mx metal, TSMC shared evaluation data of metal lines with and without the DoD process.  The graphs below show there was no impact to metal line resistance or TDDB/electromigration reliability.

Summary

Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error.  The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material.  The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability.  This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

Hopefully, selective ALD flows will transition soon from R&D to production fabrication – the potential impact of this chemistry for advanced node scaling is great.

-chipguy

References

[1]   Chen, H.-P., et al, “Fully Self-Aligned via Integration for Interconnect Scaling Beyond 3nm Node”, IEDM 2021, paper 22-1.

Note:  All images are copyright of the IEEE.

 

Posted on

Technology Design Co-Optimization for STT-MRAM

Technology Design Co-Optimization for STT-MRAM
by Tom Dillinger on 01-04-2022 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

sense amplifier

Previous SemiWiki articles have described the evolution of embedded non-volatile memory (eNVM) IP from (charge-based) eFlash technology to alternative (resistive) bitcell devices.  (link, link)

The applications for eNVM are vast, and growing.  For example, microcontrollers (MCUs) integrate non-volatile memory for a variety of code and data storage tasks, from automotive control to financial bankcard security to IoT/wearable sensor data processing.  The key characteristics of eNVM are:

  • performance (read access time, write-verify cycle time)
  • data retention, over voltage and (especially) temperature extremes
    • bitcell “drift” over time (e.g., changes in device resistance leading to increasing bit-error rate)
  • write endurance (# of write cycles)
  • reliability (e.g., susceptibility to bit storage fails from external radiation or magnetic fields)
  • sensitivity to process variability
  • cost (e.g., # of additional mask lithography steps, compatibility of the embedded memory fabrication with existing FEOL and BEOL process steps)

(Note that the number of extra masks for embedded flash is large, and requires exposure to high programming voltage.)

  • yield (assume a double-error correction data width encoding will be used)

STT-MRAM

One of the leading eNVM technologies is the magnetic tunnel junction (MTJ) device, which uses a spin-torque transfer write current mechanism to toggle the MTJ between “parallel” (P) and “anti-parallel” (AP) states.  During a read cycle, the resistance differences between these states is sensed.

The figure below illustrates the process integration of STT-MRAM into a BEOL process for an advanced logic node. [1]

This STT-MRAM process offers a considerable cost advantage over scaling existing eFlash device technology.

In the image on the right above, the word lines run through the array connected to access devices.  During a read cycle, the column select line is grounded, and the resistance of the active MTJ determines the bitline current.  For a write cycle, since the MTJ programming current flows in opposite directions for a write to the AP state versus a write to the P state, the roles of the bitlines and column select lines are reversed, depending on the data value – i.e., write_1:  BL = 0V, CS = VPP;  write_0: BL = VPP, CS = 0V.

STT-MRAM technology does present some challenges, however.

  • small read sensing window

The read cycle needs to sense the difference in MTJ resistance between parallel and anti-parallel states.  Process variation in MTJ characteristics results in narrowing of this resistance contrast.  Sophisticated sense amplifier design methods are needed to compensate for a tight resistance margin.

  • strong MTJ sensitivity to temperature

The embedded MTJ IP will be subjected to temperature extremes both during assembly and during its operational lifetime.  The solder ball reflow and package-to-PCB attach process temperature is far higher than the maximum operational temperature, albeit only once and for a relatively short duration.  (Solder reflow temperatures are ~245C-260C.)  The operational environment for the demanding nature of MCU applications typically spans -40C to 125C.  The composition and diameter of the MTJ materials – i.e., the fixed and free magnetic layers, the tunneling oxide – are selected to maintain the spin-transfer torque properties throughout both assembly and operating temperature cycles.

Yet, due to the MTJ sensitivity to temperature, any attempt to pre-program data into the embedded STT-MRAM array prior to exposure to the assembly process temperatures would be fruitless.  Special technology-design co-optimization (TDCO) methods are needed to initialize (a portion of) the STT-MRAM array with key data measured at wafer test – more on these methods shortly.

Also, the read sensitivity – i.e., the resistance difference of P and AP states – is reduced at high temperature.  At cold temperature, the write current required to set the state of the bitcell is increased.  Again, TDCO techniques are required to compensate for these reduced margins at different temperature extremes.

  • process variation in MTJ characteristics

Sensing of the resistance differential also needs to address the process variation in MTJ devices, and the range of P and AP resistance states.

At the recent International Electron Devices Meeting (IEDM) conference in San Francisco, TSMC presented their TDCO approaches to address the STT-MRAM challenges above. [2] The rest of this article summarizes the highlights of their presentation, leading to the production release of STT-MRAM IP in their N22 ultra-low leakage process (N22ULL) node.

TSMC TDCO for N22ULL STT-MRAM

  • read sensing

When an address word line is raised along a set of bitcells in the MRAM array, current flows through the MTJ from the (pre-charged) bitline to the (grounded) select line.  The magnitude of the current on the bitline depends upon the P or AP state of the individual bitcell, and needs to be accurately sensed.  The MTJ process variation across the array suggests that each bitline sense circuit must be individually “trimmed” to match the specific local characteristics of the devices.  And, the strong temperature dependence of the MTJ needs to be dynamically compensated.

The optimized TSMC solution to MRAM bitline read sensing is illustrated below.

The read sense circuitry shown above is differential in nature, intended to amplify the voltage difference on lines Q and QB that evolves during the read cycle.  Prior to the start of the read, both nodes Q and QB are pre-charged.  When the address word line is raised, bitline current flows through the MTJ – in the figure above that is represented by current source Icell.

Note that the bitcells in the memory array are “single-ended” – i.e., there is only one connection to the sense amplifier.  (This is in contrast to a conventional 6T SRAM bitcell, for example, which provides connections to both Q and QB of the sense amplifier.)  As a result of the single connection, it is necessary to provide the QB line with a reference current, which needs to be between the Icell_P and Icell_AP values which may be flowing in the opposite side of the sense amplifier.  Further, this reference current needs to adapt to the local die temperature.

TSMC developed a unique design approach to provide the Iref value to a set of N bitcells + sense amplifiers on a word line in the array.

The figure above depicts N/2 reference MTJs that have been initialized to a P resistive state and N/2 reference MTJs in an AP state.  Their outputs have been dotted to provide a “merged” reference current.  The WL_REF signal is raised in a balanced timeframe as the active wordline – the resulting merged reference current is connected to the N sense amplifiers.  As a result, the Iref current to an individual SA is:

  ((N/2) * I_P) + ((N/2) * I_AP) / N = (I_P + I_AP) / 2

or the ideal “midpoint” current on the QB line.  After an appropriate duration into the read cycle, when a Q and QB voltage difference has been established, the Latch enable signal is raised to amplify the differential and drive Dout to the read value.

The approach to generate Iref for the sense amplifiers in an MRAM array bank provides both temperature compensation and some degree of “averaging” over process variation.

  • sense amplifier trimming

Nevertheless, MTJ process variation necessitates a per-sense amplifier correct design technique.  In the sense amplifier circuit figure above, devices N1A through N1X are in parallel with the sense pulldown transistor, all connected to Vclamp.  The switches in series with these devices represent the capability to trim the resistance of the Q line during a read cycle.  (The N2A through N2X devices provide a comparable, symmetric capability on the QB line, matching the loading on the Q line.)  During wafer-level testing, the memory BIST macro IP includes programming support to adjust the “trim code” to realize the lowest number of bit read failures during BIST, with error-correction circuitry disabled.  (This testing is performed at elevated temperature.)

  • OTP-MRAM

It was mentioned earlier that the elevated temperatures to which the MTJ is subjected during assembly preclude any attempt to write data into the array during die test.  Yet, the trim code values for each sense amplifier derived during memory BIST need to be retained in the array.  (Also, any built-in array self-repair BISR codes identified after BIST testing need to be stored.)

To address this issue, TSMC developed a unique approach, where some of the MTJ cells are subjected to a one-time programming (OTP) write sequence.  These cells retain their OTP values after exposure to the solder-reflow assembly temperature.

For these storage locations, a (tunnel oxide) “breakdown” voltage is applied to the MTJ to represent a stored ‘0’ value; the cell current will be high.  As illustrated above, any OTP junction that does not receive an applied breakdown voltage during programming will remain (P or AP) resistive, and thus will be sensed as storing a fixed ‘1’ value.

  • temperature-compensated write cycle

Whereas the sense amplifier (Rp versus Rap) read margin is reduced at high temperature, the MTJ write cycle is a greater challenge at low temps, where higher current are required to alter the MTJ state.  TSMC developed an operational write-verify cycle, where the applied write voltage is dynamically adapted to temperature.  The figure below shows a shmoo plot indicating the (wordline and bitline) write voltage sensitivity versus temperature (for AP-to-P and P-to-AP), and thus the need for compensation.

TSMC noted the “wakeup time” of the analog circuitry used to generate the corresponding write voltages adds minimally to the write cycle time.

Summary

At advanced process nodes, STT-MRAM IP offers an attractive evolution from eFlash for non-volatile storage – e.g., high retention, high durability, low additional process cost.  TSMC recently presented their TDCO approach toward addressing the challenges of this technology, adopting several unique features:

  • improved read sensing between Rp and Rap
    • derivation of read sense amplifier reference current compensated for temperature, with process variation averaging
    • per sense amplifier “trimming” for optimal read bit error rate
  • one-time programming cell storage prior to solder reflow assembly, to retain trim codes and array repair values
  • a temperature-compensated write voltage applied to the MTJ (as part of the write-verify cycle)

The characteristics and specs for the TSMC N22ULL STT-MRAM IP are appended below.

To quote TSMC, “Each emerging memory technology has its own unique advantages and challenges.  Design innovation is essential to overcome the new challenges and bring the memory IP to market.”

-chipguy

References

[1] Shih, Yi-Chun, et al., “A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process”, IEDM 20, paper 11.4.

[2] Chih, Yu-Der, et al., “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications”, IEDM 2021, paper 2.4.

Note:  All images are copyright of the IEEE.

 

Posted on

Advanced 2.5D/3D Packaging Roadmap

Advanced 2.5D/3D Packaging Roadmap
by Tom Dillinger on 01-03-2022 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

SoIC futures

Frequent SemiWiki readers are no doubt familiar with the advances in packaging technology introduced over the past decade.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, TSMC gave an insightful presentation sharing their vision for packaging roadmap goals and challenges, to address the growing demand for greater die integration, improved performance, and higher interconnect bandwidth.[1]  This article summarizes the highlights of the presentation.

Background

2.5D packaging

2.5D packages enable multiple die to be laterally positioned in close proximity, with signal redistribution interconnect layers (RDL) between the die fabricated on a silicon interposer present between the die and package substrate.  Through silicon vias (TSVs) provide the connectivity to the substrate.

The TSMC implementation of this technology is denoted as Chip-on-Wafer-on-Substrate (CoWoS), as was introduced a decade ago using multiple FPGA die in the package to expand the effective gate count.

The emergence of high bandwidth memory (HBM) stacked die as a constituent of the 2.5D integration offered system architects with new alternatives for the memory hierarchy and processor-to-memory bandwidth.

The development investment in 2.5D technology grew, now enabling the silicon interposer area to greatly exceed the “1X maximum” reticle size, to accommodate more (and more diverse) processing, memory and I/O die components (aka, “chiplets”).

Additional package fabrication steps incorporate local “trench capacitors” into the interposer.  Oxide-poly-oxide-poly material layers fill the trench, with the poly connected to the RDL supply metal.  The resulting decoupling capacitance reduces power supply droop considerably.

Alternative technologies have also been developed, replacing the full area silicon interposer with a local “silicon bridge” (CoWoS-L) between adjacent die embedded in an organic interposer, thus reducing cost (albeit with relaxed RDL interconnect dimensions).

Concurrently, for very low cost applications, the demand for higher I/O count die than could be supported with the conventional wafer-level chip-scale package (WLCSP) led to the development of a novel technology that expands the die surface area with a “reconstituted wafer”, on which the redistribution to a larger number of I/O bumps could be fabricated.

This Integrated FanOut (InFO) technology was originally developed for single die (as a WLCSP-like offering).  Yet, the application of this technique is readily extended to support the 2.5D integration of multiple heterogeneous die placed adjacent, prior to the reconstitution step. (The InFO_oS technology will be discussed shortly.)

3D die stacking

3D die stacking technology has also evolved rapidly.  As mentioned above, the fabrication of TSVs spanning between layers of DRAM memory die with “microbumps” attached at the other end of the TSV has enabled impressive levels of vertical stacking – e.g., eight memory die plus a base logic controller die in an HBM2e configuration.

Similarly, through-InFO vias (located outside the base die in the reconstituted wafer material) has enabled additional micro-bumped die to be vertically stacked above the base InFO die – e.g., a memory die on top of a logic die.

The most recent advancement in 3D stacking technology has been to employ bump-less “direct bonding” between two die surfaces.  Applying a unique thermal + compression process, two die surfaces are joined.  The metal pad areas on the different die expand to form an electrical connection, while the abutting dielectric surfaces on the two die are bonded.  Both face-to-face (F2F) and face-to-back (F2B) die orientations are supported.  The planarity and uniformity (warpage) requirements of the surfaces are demanding; particulates present on the surface are especially problematic.  TSMC denotes their 3D package technology as System-on-Integrated Chips, or “SoIC”.

As product architects are exploring the opportunities available with these packaging technologies, there is growing interest in combining “front-end” 3D stacked SoIC configurations with 2.5D “back-end” (InFO or CoWoS) RDL patterning and assembly.  The collective brand that TSMC has given to their entire suite of advanced packaging offerings is “3D Fabric”, as illustrated below.

TSMC 3D Fabric Roadmap

At IEDM, TSMC shared their strategy for improving performance, power efficiency, signal bandwidth, and heat dissipation for these technologies.  (The majority of the focus was on bonding technology for SoIC.)

CoWoS (2.5D)

    • increase package dimensions to 3X maximum reticle size for the Si interposer
    • expectation is that stacked SoIC die will be integrated with multiple HBM stacks

InFO_oS (2.5D)

The original InFO offering was as an evolution to WLCSP, first as a single die, and then as a base die with another added on top connected to the through-InFO vias.  TSMC is also expanding the InFO offering to support multiple adjacent die embedded in the reconstituted wafer; the RDL layers are then fabricated and microbumps added for attach to a substrate (InFO-on-Substrate, of InFO_oS).  A projection for the InFO_oS configurations to be supported is illustrated below.

SoIC (3D)

The roadmap for 3D package development is shown below, followed by a table illustrating the key technical focus – i.e., scaling the bond pitch of the (F2F or F2B) stacked connections.

The bond pitch (and other metrics) for microbump technology evolution are included with the SoIC direct bonding measures in the table above for comparison.

As shown in the table above, TSMC has defined a new (relative comparison) metric to represent the roadmap for 3D stack bonding technology – an “Energy Efficiency Performance” (EEP) calculation.  Note that the target gains in EEP are driven by the aggressive targets for scaling of the bond pitch.

EEP = (bond_density) * (performance) * (energy efficiency)

Much like the IC scaling associated with Moore’s Law, there are tradeoffs in 3D bond scaling for performance versus interconnect density.  And, like Moore’s Law, the TSMC roadmap goals are striving for a 2X improvement in EEP for each generation.

SoIC Futures

As an illustration of the future potential for 3D stacking, TSMC provided an example of a three-high stacked structure, as shown below.

Note that the assumption is that future HBM stacks will migrate from a microbump attach technology within the stack to a bonded connection – the benefits of this transition on performance, power, and thermal resistance (TR) are also shown in the figure.

heat dissipation

Speaking of thermal resistance, TSMC emphasized the importance of both the bonding process for low TR and design analysis of the proposed 3D stack configuration, to ensure the junction temperature (Tj) across all die remains within limits.

The IEDM presentation referred to additional research underway at TSMC to evaluate liquid-cooling technology options. [2] As illustrated below, “micro-pillars” can be etched into a silicon lid bonded to the assembly, or even directly into the die, for water cooling.

Summary

Advanced 2.5D and 3D packaging technologies will provide unique opportunities for systems designers to optimize performance, power, form factor (area and volume), thermal dissipation, and cost.  TSMC shared their development roadmap for both 2.5D and 3D configurations.

The 2.5D focus will remain on support of larger substrate sizes for more (heterogeneous) die integration;  for markets focus on cost versus performance, different interposer/bridge (CoWoS) and reconstituted wafer (InFO technology options are available.

3D stacking technology will receive the greatest development focus, with an emphasis on scaling the interface bond pitch.  The resulting “2X improvement in EEP” for each SoIC generation is the target for the new “More than Moore” semiconductor roadmap.

-chipguy

References

[1] Yu, Douglas C.H., et al, “Foundry Perspectives on 2.5D/3D Integration and Roadmap”, IEDM 2021, paper 3-7.

[2]  Hung, Jeng-Nan, et al., “Advanced System Integration for High Performance Computing with Liquid Cooling”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), p. 105-111.

Note:  All images are copyright of the IEEE.

Posted on

US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight

US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight
by Craig Addison on 11-14-2021 at 6:00 am
Categories: China, Foundries, TSMC

China TSMC Supply chain woes 2021
Chinese state-run media blames Taipei for allowing Taiwan Semiconductor Manufacturing Co to submit chip supply information to the US government. Photo: Shutterstock

TSMC drew the ire of Chinese state media last week after it complied with the US Department of Commerce request to submit supply chain data by the November 8 deadline.

The Chinese reports, which called it an act of “surrender” to US hegemony, were careful in laying blame on Taipei for caving in to Washington, rather than pointing fingers at TSMC itself.

Chinese state media commentators are experts in party propaganda, not semiconductors, so they could be excused for not knowing the obvious: TSMC didn’t become the world’s leading foundry by blabbing about what its customers are doing.

Separately, Reuters quoted TSMC saying that it did not disclose any detailed confidential customer information to the US.

TSMC was one of 23 entities, including ASE, Infineon, Micron and Philips, that provided supply chain data, with most chipmakers choosing to do so privately rather than publicly disclosing their data.

But there were some interesting nuggets to be found in the public submissions.

On the customer side, Philips revealed that it had to delay 13 per cent of its production due to the semiconductor shortage. It added that the most severe shortages were in MCUs, FPGAs, ASICs, memory, linear and discretes – and that sourcing hard-to-find components now takes 12 to 18 months compared to 3 months in normal times.

Technicolor was something you’d see on movie screens in the golden days of Hollywood. These days it is the trading name of a French based company (formerly Thomson) that provides, among other things, visual effects production services for movies. It also buys chips, but not anywhere near the quantity of a giant like Philips – and therein lies the problem.

As a small customer, Technicolor has little clout amid product shortages, and it expressed those frustrations in its submission.

“Technicolor’s IC supply chain visibility has been challenged and remains uncertain, with unstable raw material supply (lead-frame, substrate), shortages with IC fabs and OSAT balancing capacity (allocation) and material availability to prioritize supply impacting delivery schedules with the fluctuation in lead-time impacting delivery commitments,” the company said.

Rising costs from foundry suppliers like TSMC and UMC was another bone of contention for the French company.

“IC suppliers are requesting customers to pay expediting fees to secure supply from foundries, and logistic fees are ever rising from our freight forwarders.  Cost increases like this are not standard in the semiconductor market and go against Moore’s Law, which is why they were not foreseeable or expected.” Ouch!

Back on the chip supply side, Infineon was blunt in telling the US government what the “root cause” for the global chip shortage was: the JIT (just-in-time) manufacturing system.

“To really overcome the global chip shortage, the JIT system should be replaced by a collaborative platform where demand information is shared anonymously (to keep the competition going) but without the bullwhip bias,” Infineon said.

The bullwhip effect refers to the demand distortion that travels upstream in the supply chain, amplified by the lack of synchronization among supply chain members.

The most damning submission, though, came from the Institute for New Economic Thinking, which slammed member companies of the Semiconductor Industry Association (SIA) like Intel and Qualcomm for asking the US government for industry funding on the one hand, but using their spare cash for stock buybacks on the other. The latter, of course, is meant to boost share prices and increase the wealth of stock-holding executives at the companies.

“Most of the SIA corporate members now lobbying for the CHIPS for America Act have squandered past support that the US semiconductor industry has received from the US government for decades by using their corporate cash to do buybacks to boost their own companies’ stock prices,” report authors William Lazonick and Matt Hopkins charged.

“Among the SIA corporate signatories of the letter to President Biden, the five largest stock repurchasers – Intel, IBM, Qualcomm, Texas Instruments, and Broadcom – did a combined $249 billion in buybacks over the decade 2011-2020, equal to 71 percent of their profits and almost five times the subsidies over the next decade for which the SIA is lobbying.”

It’s not only chipmakers that do this. The Semiconductors in America Coalition (SIAC) was formed in May to lobby Congress for the passage of the CHIPS act. Members include Apple, Microsoft, Cisco and Google, who spent a combined $633 billion on buybacks during 2011-2020, according to the report, which pointed out this was about 12 times the proposed government subsidies under CHIPS to support wafer fabs on US soil.

“If the Congress wants to achieve the legislation’s stated purpose of promoting major new investments in semiconductors, it needs to deal with this paradox,” the report authors said.

Their suggestion: require the SIA and SIAC to extract pledges from members to end stock buybacks as open-market repurchases over the next 10 years.

Any bets on how the members will vote on that?

The Chip Warriors podcast series

Posted on

Taiwan Semiconductor Outlook May 1988

Taiwan Semiconductor Outlook May 1988
by Daniel Nenni on 11-12-2021 at 6:00 am
Categories: Events, Foundries, TSMC
6 Comments

James E. Dykes

This is an interesting piece of TSMC history. From 1987 to 1988 James E. Dykes served as the first President and Chief Executive Officer of Taiwan Semiconductor Manufacturing Company Ltd.

Taiwan Semiconductor Outlook
by James E. Dykes
President & Chief Executive Officer
Taiwan Semiconductor Manufacturing Company

Given at:

Fourth Annual In-Stat Inc. Semiconductor Forum

Held at the Pointe at South Mountain.
Phoenix, Arizona
Monday, May 2, 1988

— Opening Comments —

As Jack said, I’m here to talk about the Taiwan semiconductor outlook.

That outlook is, in a word, great.

The Economist Magazine, in its March 5 issue, called Taiwan and its nearly 20 million people “The most dynamic country in east Asia.” And it’s all true. The country is going through a rare and rapid period of enlightenment.

Politically, martial law has been lifted, newspaper censorship and control have been revised, and new political reforms are expected to continue under President Lee Teng-hui, who took office in January after the death of President Chiang Ching-kuo.

Economically, productivity is rising at a record rate. In 1952, for example, per capita GNP was $48. Today it’s more than $5,000 and next year, it’s projected to be more than $6,000. In response to U.S. trade pressures, import tariffs across a whole range of goods are being sharply reduced. And Taiwan’s foreign exchange reserves exceed $75 billion, the world’s third largest after Japan and west Germany. All this in a country with few natural resources.

Yet to really understand the impact Taiwan will have on the semiconductor industry, you have to know why the country is in transition. For a variety of reasons, Taiwanese manufacturers are heading upmarket across a whole range of industries and leaving behind their image as manufacturers of cheap, shoddy, or imitation goods.

Korea and Taiwan are often mentioned as exhibiting the same trends, but the driving forces are quite different. Korea is dominated by large, vertically integrated companies, the chaebol, with massive government investment and direction for strategic industries.

Taiwan, by comparison, is more like Silicon Valley. You find in Taiwan the same entrepreneurial spirit the same willingness to trade hard work for business success and the opportunities to make it happen, that you find in Santa Clara County, and here in the Valley of the Sun. Even Taiwan’s version of Wall Street will seem familiar to many of you. There’s a red-hot stock market where an entrepreneur can take a company public and become rich overnight.

The Taiwanese people are hard-working and well-educated. One in every four is a student and the literacy rate is 91%. Society as a whole is stable and is becoming more affluent, the average family income last year of over $18,000 is projected to rise to more than $40,000 in the early 1990s. Yet the nation’s wealth is distributed fairly equitably, with the wealthiest 20% of households having an income less than five times that of the poorest 20%.

The society is becoming more cosmopolitan. Three-quarters of the population now live in urban areas and agriculture as a percentage of gross domestic product has dropped from about one-third in 1952 to about than one-twentieth today.

During the same time period, the percentage of industrial output more than doubled and now accounts for about half of GDP.

Taiwan, as a whole, has a GNP of about $98 billion, but the more telling economic statistics have to do with the volume and type of foreign trade. Because the country’s economic growth has been fueled largely by exports and Taiwan now faces a different set of export conditions.

In 1953, Taiwan’s overall foreign trade amounted to $320 million. In 1986, total foreign trade amounted to about $64 billion, and the country ran a $16.6 billion surplus with the U.S., its largest trading partner.

Overall, Taiwan’s trade surplus was about $19 billion.

As I said earlier, Taiwan has foreign exchange reserves of more than $75 billion. But it has a foreign debt of only about $3 billion. And as you know, Taiwan’s rising trade surplus has brought U.S. protests. including a decision by the U.S. administration to remove Taiwan from the generalized system of preferences program, which exempts selected countries and product categories from U.S. import tariffs.

In response to the overall trade situation, Taiwan has acted in a number of areas, reducing its own import tariffs on a range of products, widening its market to foreign goods and services and spending more on capital-intensive domestic public-works projects. Even boating and coastal fishing are being opened and targeted as tourist attractions.

Currency exchange rates are also changing the nature of many Taiwanese enterprises. Over the last few years, the Taiwan dollar has appreciated dramatically against the U.S. dollar, nearly 20% in 1987 alone. Clearly, Taiwan is losing its edge as a source of low-cost labor.

The government is actively encouraging Taiwanese companies to look for more domestic markets, to find export opportunities in countries other than the U.S., to move upmarket, to products of greater sophistication with greater added-value and competitive worth and to increase R&D expenses.

The electronics industry accounted for 4.2% of Taiwan’s GNP last year and 20% of the value of exports. Planners talk about raising the proportion of such technology-intensive industries from the current 24% to 35% of the manufacturing sector by next year.

You can look at semiconductors as a microcosm of this overall trend.

While the Taiwanese have historically served the labor-intensive test and assembly segments, they are moving upmarket into silicon integrated circuit production. The value of ICs shipped from 1979 to 1985 grew by almost 195%, from $133 million to $391 million.

The value of transistor shipments grew by an impressive but smaller 111%, while growth in the value of low-technology diodes and capacitors remained virtually flat in the same time period.

The emphasis is obviously changing. As you know, semiconductor consumption is a barometer of end-use electronics production. According to Dataquest, last year total Taiwan semiconductor consumption was about $1.1 billion out of a worldwide $37 billion. This year, Taiwan’s semiconductor consumption is projected to rise by 31.5%, versus 20% worldwide. In dollar terms, Taiwan’s share is expected to grow to more than $3 billion over the next five years for a compound annual growth rate of 22.5%.

The major chip end-users in Taiwan are manufacturers of personal computers and associated products and consumer electronics equipment chiefly VCRs and TVs. Broken down by segment, the personal computer area will show 22.3% compound annual growth in the next five years, followed by the VCR segment at 11%, and TV production at about 8.5%.

Two trends here underscore the move upmarket from test and assembly activities: one, the Japanese are moving production of high-performance consumer electronics to Taiwan, and two, the government is encouraging Taiwanese companies to develop their own manufacturing skills in products with high growth potential: CDs, digital TV, digital audio tape.

The semiconductor industry in Taiwan is beginning to blossom. It’s interesting to note that although Taiwan’s growth as a semiconductor supplier was fueled largely by foreign firms until the early 1980s. The island’s first semiconductor factory for transistors was started in 1963 by a native Chinese with technology developed at Cheng Kung University.

Following that, of course, there was a virtual explosion of discretes production, beginning with general instrument, which established a facility for germanium transistors in 1965. That was soon followed by investments in assembly facilities by Texas Instruments and American Microsystems, and later by a host of others.

By 1984, there were 57 companies and organizations in semiconductors, 13 of them in ICs, and 44 in discretes and optoelectronics.

The Hsinchu Science Park, where we are based, is home to an increasing critical mass of semiconductor companies alongside other firms engaged in electronics design and production, there are about 70 high-technology companies located there today. The concept is to have semiconductor producers and customers in the same industrial complex.

Let me describe the IC-related firms in Taiwan. Besides ERSO, the governmental electronic research service organization, there are eight firms with wafer and/or IC manufacturing capability. They are TSMC, United Microelectronics Corporation, or UMC, Vitelic, Mosel, Quasel, Hualon, Winbond, and UTIC.

Taiwan has a combined capability to produce 61,000 4-inch wafers per month now.

But with already announced expansion plans, by 1990 Taiwanese producers will have the additional monthly capability for 80,000 6-inch wafers and 35,000 5-inch wafers.

There are more than 40 new design houses, like STK, Holtek, and Silicon Integrated Systems. ERSO serves as a photomask supplier and a new mask shop is now being incorporated. It’s called Taiwan Mask Corporation and it will consist of the ERSO facilities now being used plus new investment in the science park for additional e-beam mask-making capability.

And of course, there are more than 30 assembly and test facilities on the island, TI, Philips, General Instrument, GE Solid State, and so on.

Dataquest ranked UMC third in 1987 as a supplier of MOS logic devices in the Asia-Pacific/rest of world market. In 1987, ERSO and UMC accounted for nearly 3% of total semiconductor production in that market 7% of total MOS production and 10% of total MOS logic devices.

Taiwan’s future IC design efforts will likely focus on ASIC circuits and CAD tools. Process options will include sub-micron CMOS, and several others: BiCMOS, CCDs, power ICs, thin-film devices, and gallium arsenide. Package development will be directed at high pin-count and multi-chip, multi-layer configurations.

However, much work remains to be done for this to happen. If Taiwan is to achieve its IC goals in the next five years, it must develop an infrastructure adequate to serve local industry needs. The most pressing need is for a locally based network of material, equipment and service suppliers to support the growth of the industry.

Let me give you a sense of that projected growth. Winbond is a maker of ICs for the personal computer, telecommunications, and consumer electronics industries. It now has sales of less than $35 million but plans to be a $100 million company by 1991 with 300 employees instead of its current 110.

It is building a class 10 wafer fab in the Science Park, with a capacity of 15,000 5-inch wafers per month. The fab will run 2-micron CMOS and NMOS processes and will be ready in September. A second fab is under serious consideration for operation in 1992.

UMC is building a new 6-inch fab to add capacity of 30,000 6-inch wafers per month. The company expects to spend about $140 million over the next three years for capacity additions.

TSMC is building a new manufacturing facility in the Science Park, with a capacity for 30,000 6-inch CMOS wafers per month, although a portion is convertible to 8-inch. The entire facility is designed for sub-micron geometries, but initial production will center on 1.2-micron feature sizes. It is geared toward turnkey production, from reticle generation to assembly and final test… And we expect it to be operational by the end of next year.

And design house SiS projects a 240% increase in sales to $68 million in 1992.

As you can see, Taiwan is growing and maturing. It is becoming a more respected competitor in the world’s economy and is leaving behind its heritage of disrespect for intellectual property rights.

There are risks and rewards for technology companies who wish to ally themselves with the most dynamic country in east Asia. The risks generally have to do with issues of technology development and availability.

The rewards generally have to do with what you might expect from dealing with a proud, talented, and hard-working people. Quality products at competitive prices and long-term, mutually beneficial relationships.

Thank you very much.

Posted on

Update on TSMC’s 3D Fabric Technology

Update on TSMC’s 3D Fabric Technology
by Tom Dillinger on 11-03-2021 at 8:00 am
Categories: Chiplet, Events, Foundries, TSMC
4 Comments

3D eTV testchip

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

Overview of 3D Fabric

The TSMC 3D Fabric advanced packaging technology spans both the 2.5D and vertical die stacking offerings, as depicted below.

The Integrated FanOut (InFO) packages utilize a reconstituted wafer consisting of die embedded face down, surrounded by a molding compound (link).

Redistribution interconnect layers (RDL) are fabricated on the epoxy wafer.  (InFO-L refers to a silicon “bridge chiplet” between die embedded in the InFO package for improved inter-die connectivity over the RDL metallization pitch.)

The 2.5D CoWoS technology integrates die (and often, high-bandwidth memory stacks) on an interposer utilizing microbump attach.  The original CoWoS technology offering (now CoWoS-S) used a silicon interposer, and related silicon-based lithography for RDL fabrication;  through-silicon vias (TSVs) provide connectivity to the package bumps.  The silicon interposer technology offers improved interconnect density, critical for the high signal count HBM interface.  More recently, TSMC has been offering an organic interposer (CoWoS-R), providing a tradeoff between interconnect density versus cost.

The 3D SoIC offering provides vertical integration utilizing hybrid bonding between die pads.  The die may be oriented in face-to-face or face-to-back configurations.  TSVs provide connectivity through the (thinned) die.

InFO and CoWoS offerings have been in high-volume production for several years.  The recent innovations in CoWoS development relate to expanding the maximum silicon interposer dimensions to greater than the maximum reticle size to accommodate a larger number of die (especially, HBM stacks), stitching together the RDL interconnects.

The majority of Jim’s presentation covered advanced in SoIC development.

SoIC Testchip

TSMC shared results of a recent SoIC qualification test vehicle, as shown below.

The configuration used was the vertical bonding of an (N5) CPU die with an (N6) SRAM die, in a face-to-back topology.  (Indeed, a major CPU vendor has pre-announced plans for a vertical “last-level” SRAM cache die attached to a CPU using TSMC’s SoIC, to be available in 1Q2022.)

SoIC Design Flow

Jim presented a high-level design flow for vertical die integration, as shown in the figure below.

The flow requires concurrent focus on both top-down system partitioning into individual die implementations, plus early analysis of the thermal heat dissipation in the composite configuration, as highlighted above.

The discussion on thermal analysis highlighted the “chimney” nature of the low thermal resistance paths of the BEOL PDN and interconnect, compared to the surrounding dielectrics, as shown above.  Specifically, TSMC has collaborated with EDA vendors on improving the accuracy of the SoIC model discretization techniques, applying a more detailed mesh in specific “hotspot” areas initially identified with a coarse grid analysis.

TSMC also presented a methodology recommendation to incorporate thermal analysis results into the calculation of SoIC static timing analysis derate factors.  Much like on-chip variation (OCV) is dependent upon the distance spanned by (clock and data) timing paths, the thermal gradient for the SoIC paths is an additional derate factor.  TSMC reported that on-die temperature gradients for a path are typically ~5-10C, and a small flat derate timing margin for temperature should suffice.  For SoIC paths, large gradients of ~20-30C are feasible.  A flat derate to cover this range would be too pessimistic for paths with a small temperature difference – results of SoIC thermal analysis should be used for derate factor calculation.

SoIC Testing

The IEEE 1838 standardization effort pertains to the definition of die-to-die interface testing (link).

Much like the IEEE 1149 standard for boundary-scan chains on-die for package-to-package testing on a printed circuit board, this standard defines the control and data signal ports on each die for post-stack testing.  The primary focus of the standard is to exercise the validity of the face-to-face bonds and TSVs introduced during SoIC assembly.

Jim indicated that this definition is sufficient for low-speed I/Os between SoIC die, yet a more extensive BIST method will be required for high-speed I/O interfaces.

TSMC Foundation IP for SoIC – LiteIO

TSMC’s library development teams commonly provide general-purpose I/O cells (GPIOs) for each silicon process node.  For the die-to-die connections in SoIC configurations, where the driver loading is less, TSMC offers a “LiteIO” design.  As illustrated below, the LiteIO design focuses on optimizing the layout to reduce parasitic ESD and antenna capacitances, to enable faster datarates between die.

EDA Enablement

The figure below lists the key tool features recently developed in collaboration with major EDA vendors for the InFO and SoIC package technologies.

Summary

TSMC continues to invest heavily in 2.5D/3D advanced packaging technology development.  The key recent initiatives have focused on the methodology for 3D SoIC direct die attach – i.e., partitioning, physical design, analysis.  Specifically, early thermal analysis is a mandatory step.  Additionally, TSMC shared results of their SoIC eTV qualification testchip vehicle.  2022 is shaping up to see the rapid emergence of 3D SoIC designs.

-chipguy

Also read:

Highlights of the TSMC Open Innovation Platform Ecosystem Forum

Highlights of the TSMC Open Innovation Platform Ecosystem Forum

 

 

Posted on

On-Chip Sensors Discussed at TSMC OIP

On-Chip Sensors Discussed at TSMC OIP
by Tom Simon on 11-02-2021 at 10:00 am
Categories: Analog Bits, Foundries, IP, TSMC

phase noise correlation

TSMC recently held their Open Innovation Platform (OIP) Ecosystem Forum event where many of their key partners presented on their latest projects and developments. This year one of their top IP provider partners, Analog Bits, gave two presentations. Analog building blocks have always been necessary as enabling technology on leading edge designs. The move to 3nm continues this important relationship. Analog Bits has developed specialized analog IP that can help differentiate end products. For instance, they have focused on optimized high performance and low power SerDes, among other things. Another significant area is specialized on-chip sensors for monitoring chip health and performance.

In his presentation Mahesh Tirupattur, Analog Bits’ EVP, discussed how their sensing IP was used by Cerebras in developing the largest chip ever designed. The Cerebras WSE-2 has 2.6 trillion transistors in 850,000 optimized cores covering 46,225 square mm of silicon.  Cerebras faced challenges in power distribution and power supply integrity. Analog Bits IP offered them a solution to monitor chip operation in real time that can be used to apply real time corrective actions. They used 840 distributed glitch detectors to provide real time coverage of the entire design. The Analog Bits glitch detectors can detect short duration events that could otherwise easily be missed. They are programmable for trigger voltage, depth of glitch and time span of glitch. Their sensitivity exceeds 5pVs.

Recently Analog Bits expanded their sensor offering by adding power supply glitch detectors with an integrated voltage reference to their lineup of integrated POR sensors and on-die PVT sensors. This allows them to cover all aspects of chip operation in real time, including POR conditions – and now the health of the power supplies.

Of course, sensors require extremely high accuracy to correctly report chip behavior. Similarly, clocking macros need accuracy to enable proper chip operation. So, it was good to see that their second presentation at OIP was specifically on the topic of design and verification of these blocks. The paper was titled “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications”, and authored by Sweta Gupta, Director of Circuit Engineering at Analog Bits and Greg Curtis, Sr. Product Manager of Siemens EDA. The paper itself was the result of a three-way collaboration between TSMC, Siemens and Analog Bits.

In the second presentation Analog Bits shared correlation data on silicon measurements to specification for several of their PLLs, a power supply droop detector and a temperature sensor. Here is one of their slides on the phase noise correlation between measurement and silicon for a PLL built in TSMCs N5.

phase noise correlation

Analog Bits has a broad and well thought out portfolio of analog IP. They have customers on a wide range of processes from 0.25um to 3nm. I am sure that part of their success stems from their no-royalty business model. They have billions of units shipped from over a thousand IP deliveries since they first started in 1995. While the OIP presentations are over, more detailed information on all of their IP for on-chip sensors, SerDes, clocks and I/Os is available by contacting them. Their website offers detailed products listings & data sheets, and access to their N5 test chip video.

Also read:

Package Pin-less PLLs Benefit Overall Chip PPA

Analog Sensing Now Essential for Boosting SOC Performance

Analog Bits is Taking the Virtual Holiday Party up a Notch or Two

Posted on

Design Technology Co-Optimization for TSMC’s N3HPC Process

Design Technology Co-Optimization for TSMC’s N3HPC Process
by Tom Dillinger on 11-02-2021 at 8:00 am
Categories: Events, Foundries, TSMC
1 Comment

N3HPC performance comparison

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

One of the topics that L.C. discussed was the initiatives that TSMC pursued for the N3 process node, specifically for the High-Performance Computing (HPC) platform.  This article provides more details about the design-technology co-optimization (DTCO) activities that resulted in performance gains for N3HPC, compared to the baseline N3 process.  These details were provided by Y.K. Cheng, Director, Design Solution Exploration and Technology Benchmarking, in his presentation entitled “N3 HPC Design and Technology Co-Optimization”. 

Background

Design technology co-optimization refers to a cooperative effort among process development engineering and circuit/IP design teams.  The technology team optimizes the device and lithography process “window”, typically using TCAD process simulation tools.  At advanced nodes, the allowed lithographic variability in line widths, spacings, uniformity, and density (and density gradient) is limited – technology optimization seeks to define the nominal fabrication parameters where the highly-dimensional statistical window maintains high yield.  The circuit design team(s) evaluate the performance impacts of different lithographic topologies, extracting and annotating parasitic R and C elements to device-level netlist models.

A key element to DTCO is pursued by the library IP team.  The standard cell “image” defines the allocated (vertical) dimension for nFET/pFET device widths and the number of (horizontal) wiring tracks available for intra-cell connections.  The image also incorporates a local power distribution topology, with global power/ground grid connectivity requirements.

In addition to the library cell image, the increasing current density in the scaled metal wires at advanced nodes implies that DTCO includes process litho and circuit design strategies for contact/via connectivity.  As the design variability in contact/via sizes is extremely limited due to litho/etch uniformity constraints, the process and circuit design teams focus on optimization of multiple, parallel contacts/vias and the associated metal coverage.

And, a critically important aspect of DTCO is the design and fabrication of the SRAM bitcell.  Designers push for aggressive cell area lithography, combined with device sizing flexibility for sufficient read/write noise margins and performance (with a large number of dotted cells on the bitlines).  Process engineers seek to ensure a suitable litho/etch window, and concurrently must focus on statistical tolerances during fabrication to support “high-sigma” robustness.

The fact that TSMC enables customers with foundation IP developed internally provides a tight DTCO development feedback loop.

N3HPC DTCO

Y.K. began his presentation highlighting the N3HPC DTCO results, using the power versus performance curves shown in the figure below.  (The reference design block used for these comparisons is from an Arm A78 core;  the curves span a range of supply voltages, at “typical” device characteristics.)

The collective set of optimizations provide an overall 12% performance boost over the baseline N3 offering.  Note that (for the same supply voltage) the power dissipation increases slightly.

Y.K. went into detail on some of the DTCO results that have been incorporated into N3HPC.  Note that each feature results in a relatively small performance gain – a set of (consistent) optimizations is needed to achieve the overall boost.

  • larger cell height

Wider nFET and pFET devices within a cell provide greater drive strength for the (high-fanout) capacitive loads commonly found in HPC architectures.

  • increase in contacted poly pitch (CPP)

A significant parasitic contribution in FinFET devices is the gate-to-source/drain capacitance (Cgd + Cgs) – increasing the CPP increases the cell area (and wire lengths), but reduces this capacitance.

  • increased flexibility in back-end-of-line (BEOL) metal pitch (wider wires), with corresponding larger vias, as illustrated below
  • high-efficiency metal-insulator-metal (MiM) decoupling capacitor topology

The MiM capacitor cross-section illustrated below depicts three metal “plates” (2 VDD + 1 VSS) for improved areal efficiency over 2-plate implementations.

Improved decoupling (and less parasitic Rin to the capacitor) results in less supply voltage “droop” at the switching activity typically found in HPC applications.

  • double-height cells

When developing the cell image, the library design team is faced with a tradeoff between cell height and circuit complexity.  As mentioned above, a taller cell height allows for more intra-cell wiring tracks to connect complex multi-stage and/or high fan-in logic functions.  (The most demanding cell layout is typically a scannable flip-flop.)  Yet, a larger cell height used universally throughout the library will be inefficient for many gates.

The DTCO activities for N3HPC led TSMC to adopt a dual-height library design approach.  (Although dual-height cells have been selectively employed in earlier technologies, N3HPC adopted more than 400 new cells.)  This necessitated extensive collaboration with EDA tool suppliers, to support image techfile definition, valid cell placement rules, and auto-place-and-route algorithms that would successfully integrate single- and double-height cells within the design block.  (More on EDA tool features added for N3HPC shortly.)

As part of the N3HPC library design, Y.K. also highlighted that the device sizings in multi-stage cells were re-designed for optimized PPA.

  • auto-routing features

Timing-driven routing algorithms have leveraged the reduced R*C/mm characteristics of upper metal layers by “promoting” the layer assignment of critical performance nets.  As mentioned above, the N3HPC DTCO efforts have enabled more potential BEOL metal wire lithography width/spacing patterns.

As shown below, routing algorithms needed enhancements to select “non-default rules” (NDRs) for wire width/spacing.  (The use of NDRs have been available for quite a while – typically, these performance-critical nets were routed first, or often, manually pre-routed. The N3HPC DTCO features required extending NDR usage as a general auto-route capability.)  The figure also depicts how via pillar patterns need to be inserted to support increased signal current.

For lower metal layers where the lithography rules are strict and NDRs are not an option, routing algorithms needed to be enhanced to support parallel track routing (and related via insertion), as shown above.

EDA Support

To leverage many of these N3HPC DTCO features, additional EDA tool support was required.  The figure below lists the key tool enhancements added by the major EDA vendors.

Summary

TSMC has made a commitment to the high-performance computing platform, to provide significant performance enhancements as part of an HPC-specific process offering.  A set of DTCO projects were pursued for N3HPC, providing a cumulative 12% performance gain on a sample Arm core design block.  The optimizations spanned a range of design and process lithography window characteristics, from standard cell library design to BEOL interconnect options to MiM capacitor fabrication.  Corresponding EDA tool features – especially for auto-place-and-route – have been developed in collaboration with major EDA vendors.

For upcoming process node announcements – e.g., N2 – it will be interesting to see what additional DTCO-driven capabilities are pursued for the HPC offering.

-chipguy

Also read: Highlights of the TSMC Open Innovation Platform Ecosystem Forum

Posted on

Highlights of the TSMC Open Innovation Platform Ecosystem Forum

Highlights of the TSMC Open Innovation Platform Ecosystem Forum
by Tom Dillinger on 11-01-2021 at 8:00 am
Categories: Events, Foundries, TSMC
1 Comment

N3 comparison

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem forum.  The talks included a technology and design enablement update from TSMC, as well as specific presentations from OIP partners on the results of recent collaborations with TSMC.  This article summarizes the highlights of the TSMC keynote from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled: “TSMC and Its Ecosystem for Innovation”.  Subsequent articles will delve more deeply into specific technical innovations presented at the forum.

TSMC OIP and Platform Background

Several years ago, TSMC defined four “platforms”, to provide specific process technology and IP development initiatives aligned with the unique requirements of the related applications.  These platforms are:

  • High-Performance Computing (HPC)
  • Mobile (including, RF-based subsystems)
  • Automotive (with related AEC-Q100 qualification requirements)
  • IoT (very low power dissipation constraints)

L.C.’s keynote covered the recent advances in each of these areas.

OIP partners are associated with five different categories, as illustrated in the figure below.

EDA partners develop new tool features required to enable the silicon process and packaging technology advances.  IP partners design, fabricate, and qualify additional telemetry, interface, clocking, and memory IP blocks, to complement the “foundation IP” provided by TSMC’s internal design teams (e.g., cell libraries, general purpose I/Os, bitcells).  Cloud service providers offer secure computational resources for greater flexibility in managing the widely diverse workloads throughout product design, verification, implementation, release, and ongoing product engineering support.  Design center alliance (DCA) partners offer a variety of design services to assist TSMC customers, while value chain aggregation (VCA) partners offer support for test, qualification, and product management tasks.

The list of OIP partners evolves over time – here is a link to an OIP membership snapshot from 2019.  There have been quite a few recent acquisitions, which has trimmed the membership list.  (Although not an official OIP category, one TSMC forum slide mentioned a distinct set of “3D Fabric” packaging support partners – perhaps this will emerge in the future.)

As an indication of the increasing importance of the OIP partner collaboration, TSMC indicated, “We are proactively engaging with partners much earlier and deeper (my emphasis) than ever before to address mounting design challenges at advanced technology nodes.”       

Here are the highlights of L.C.’s presentation.

N3HPC

In previous technical conferences, TSMC indicated that there will be (concurrent) process development and foundation IP releases focused on the HPC platform for advanced nodes.

The figures below illustrate the PPA targets for the evolution of N7 to N5 to N3.  To that roadmap, TSMC presented several design technology co-optimization (DTCO) approaches that have been pursued for the N3HPC variant.  (As has been the norm, the implementation of an ARM core block is used as the reference for the PPA comparisons.)

Examples of the HPC initiatives include:

  • taller cells, “double-high” standard cells

N3HPC cells adopt a taller image, enabling greater drive strength.  Additionally, double-high cells were added to the library.  (Complex cells often have an inefficient layout, if confined to a single cell-height image – although double-high cells have been used selectively in previous technologies, N3HPC adopts a more diverse library.)

  • increasing the contacted poly pitch (CPP)

Although perhaps counterintuitive, increasing the cell area may offer a performance boost by reducing the Cgs and Cgd parasitics between gate and S/D nodes, with M0 on top of the FinFET.

  • an improved MiM decoupling capacitance layout template (lower parasitic R)
  • greater flexibility – and related EDA auto-routing tool features – to utilize varied (wider width/space) pitches on upper-level metal layers)

Traditionally, any “non-default rules” (NDRs) for metal wires were pre-defined by the PD engineer to the router (and often pre-routed manually);  the EDA collaboration with TSMC extends this support to decisions made automatically during APR.

Note in the graph above that the improved N3HPC performance is associated with a slight power dissipation increase (at the same VDD).

N5 Automotive Design Enablement Platform (ADEP)

The requirements for the Automotive platform include a more demanding operating temperature range, and strict reliability measures over an extended product lifetime, including:  device aging effects, thermal analysis including self-heating effects (SHE), and the impact of these effects on electromigration failure.  The figure below illustrates the roadmap for adding automotive platform support for the N5 node.

Cell-aware internal fault models are included, with additional test pattern considerations to reduce DPPM defect escapes.

RF

RF CMOS has emerged as a key technology for mobile applications.  The figure below illustrates the   process development roadmap for both the sub-6GHz and mmWave frequency applications.  Although N16FFC remains the workhorse for RF applications, the N6RF offering for sub-6GHz will enable significant DC power reduction for LNAs, VCOs, and power amplifiers.

As for the Automotive platform, device aging and enhanced thermal analysis accuracy are critical.

N12e sub-Vt operation

A major initiative announced by L.C. related to the IoT platform.  Specifically TSMC is providing sub-Vt enablement, reducing the operating supply voltage below device Vt levels.

Background – Near-Vt and Sub-Vt operation

For very low power operation, where the operating frequency requirements are relaxed (e.g., Hz to kHz), technologists have been pursuing aggressive reductions in VDD – recall that active power dissipation is dependent upon (VDD**2).

Reducing the supply to a “near-Vt” level drops the logic transition drive current significantly;  again, the performance targets for a typical IoT application are low.  Static CMOS logic gates function at near-Vt in a conventional manner, as the active devices (ultimately) operate in strong inversion.  The figure below illustrates the (logarithmic) device current as a function of input voltage – note that sub-Vt operation implies that active devices will be operating in the “weak inversion” region.

Static, complementary CMOS gates will still operate correctly at sub-Vt levels, but the exponential nature of weak inversion currents introduces several new design considerations:

  • beta ratio

Conventional CMOS circuits adopt a (beta) ratio of Wp/Wn to result in suitable input noise rejection and balanced RDLY/FDLY delays.  Commonly, this ratio is based on the strong inversion carrier mobility differences between nFET and pFET devices.  Sub-Vt circuit operation depends upon weak inversion currents, and likely requires a different approach to nFET and pFET device sizing selections.

  • sensitivity to process variation

The dependence of the circuit behavior on weak inversion currents implies a much greater impact of (local and global) device process variation.

  • high fan-in logic gates less desirable

Conventionally, a high ratio of Ion/Ioff is available to CMOS circuit designers, where Ioff is the leakage current through inactive logic branches.  In sub-Vt operation, Ion is drastically reduced;  thus, the robustness of the circuit operation to non-active leakage current paths is less.  High fan-in logic gates (with parallel leakage paths) are likely to be excluded.

  • sub-Vt SRAM design considerations

In a similar manner, the leakage paths present in an SRAM array are a concern, both for active R/W cell operation and inactive cell stability (noise margins).  In a typical 6T-SRAM bitcell, with multiple dotted cells on a bitline, leakage paths are present through the access transistors of inactive word line rows.

A read access (with pre-charged BL and BL_bar) depends on a large difference in current on the complementary bitlines through only the active word line row array locations.  In sub-Vt operation, this current difference is reduced (and also subject to process variations, as SRAMs are often characterized to a high-sigma tail of the statistical distribution curve).

As a result, the number of dotted cells on a bitline would be extremely limited.  The schematic on the left side of the figure below illustrates an example of a modified (larger) sub-Vt SRAM bitcell design, which isolates the read operation from the cell storage.

  • “burst mode” operation for IoT

IoT applications may have very unique execution profiles.  There are likely long periods of inactivity, with infrequent “burst mode” operations requiring high performance for a short period of time.  In conventional CMOS applications, the burst mode duration is comparatively long, and a dynamic-voltage frequency-scaling (DVFS) approach is typically employed by directing a DC-to-DC voltage regulator to adjust its output.  The time required for the regulator to adapt (and the related power dissipation associated with the limited regulator efficiency) are rather inconsequential for the extended duration of the typical computing application in burst mode.

Such is not the case for IoT burst computation, where power efficiency is utmost and the microseconds required for the regulator to switch is problematic.  The right hand side of the figure above depicts an alternative design approach for sub-Vt IoT CMOS, where multiple supplies are distributed and switched locally using parallel “sleep FETs” to specific blocks.  A higher VDD would be applied during burst mode, returning to the sub-Vt level during regular operation.

TSMC is targeting their initial sub-Vt support to the N12e process.  The figure below highlights some of the enablement activities pursued to provide this option for the IoT platform.

TSMC hinted that the N22ULL process variant will also receive sub-Vt enablement in the near future.

L.C. also provided an update on the TSMC 3D Fabric advanced packaging offerings – look for a subsequent article to review these technologies in more detail.

Summary

TSMC provided several insights at the recent OIP Ecosystem forum:

  • HPC-specific process development remains a priority (e.g., N3-HPC).
  • The Automotive platform continues to evolve toward more advanced process nodes (e.g., N5A), with design flow enhancements focused on modeling, analysis, and product lifetime qualification at more stringent operating conditions.
  • Similarly, the focus on RF technology modeling, analysis, and qualification continues (e.g., N6RF).

and, perhaps the most disruptive update,

  • The IoT platform announced enablement for sub-Vt operation (e.g., N12e).

-chipguy

Also read: Design Technology Co-Optimization for TSMC’s N3HPC Process

Posted on

TSMC Arizona Fab Cost Revisited

TSMC Arizona Fab Cost Revisited
by Scotten Jones on 10-13-2021 at 8:00 am
Categories: Foundries, Semiconductor Services, TechInsights, TSMC
16 Comments

TSMC North America Fabs

Back in May of 2020 I published some comparisons of the cost to run a TSMC fab in Arizona versus their fabs in Taiwan. I found the fab operating cost based on the country-to-country difference to only be 3.4% higher in the US and then I found an additional 3.8% because of the smaller fab scale. Since that time, I have continued to encounter reports that the US fab costs are approximately 30% higher than countries in Asia. In the studies I have found, most of the cost difference is attributed to “incentives” without a clear explanation of what the incentives are. My calculation does not include incentives but still the size of the difference led me to completely reexamine my assumptions and look into incentives, what they could be and how they would impact the costs I calculate.

Profit and Loss

At the highest-level companies are judged by their Profit and Loss (P&L) and I decided to go through a simple P&L line by line and look at every country-to-country difference that could impact the bottom line profitability.

A P&L is summarized on an income statement, a simple income statement is:

  1. Revenue – the money received from selling the product
  2. Cost of Goods Sold (COGS) – the direct costs to produce the product being sold. This is what our Models calculate.
  3. Gross Margin = Revenue – COGS. For wafer sale prices we estimate gross margin and apply it to the wafer cost.
  4. Period expenses – Research and Development expenses (R&D), Selling, General and Administration expenses (SG&A) and other expenses.
  5. Operating Income = Gross Margin – Period Expenses
  6. Income Before Tax = Operating Income – Interest and Other
  7. Net Income = Income Before Tax – Tax (tax is based on Income Before Tax)

We can then go through this line by line to look at country by country differences. These line numbers will be referenced below in bold/italics.

For a cost evaluation line 1. Is irrelevant.

Line 2. (COGS) Is a key differentiator.

Cost of Goods Sold

In our Models we break out wafer cost categories as follows:

  • Starting Wafer
  • Direct labor
  • Depreciation
  • Equipment Maintenance
  • Indirect Labor
  • Facilities
  • Consumables

Starting wafers – our belief is that starting wafers are globally sourced and the country where they are purchased does not impact the price. This has been confirmed in multiple expert interviews including by wafer suppliers.

Direct Labor (DL) – all our Models have DL rates by country and year for 24 countries. In 2021 the difference in labor rate from the least expensive to most expensive country was 21x! For each wafer size and product type we have estimates of labor hours required and we calculate the direct labor cost. We believe this calculation accurately reflect cost differences between countries in all our Models. It should be noted here, that leading edge 300mm wafer fabs are so highly automated that there are very few labor hours in the process and even with a huge labor rate difference, the percentage impact on wafer cost is small.

Depreciation – this is the most complex category. The capital cost to build a wafer fab is depreciated over time to yield with the depreciation amount charged off to the P&L.

We break out the capital cost to build a facility into:

  1. Equipment – we believe equipment is globally sourced and the cost is basically the same in any country. We did get one input that the US cost are slightly higher due to import costs, but we don’t believe this is significant.
  2. Equipment Installation – install costs in our Models are based on equipment type with different costs assigned to; inspection and metrology equipment, lithography equipment, and other equipment types (ALD, CVD, PVD, etc.). What we have found in our interviews is the costs vary by country with the variation being different for the different categories. For example, inspection and metrology equipment installation is heavily weighted toward electrical work that varies in cost between countries. Other equipment is more heavily weighted toward process hookups that are less country dependent. Lithography equipment is intermediate between the two.
  3. Automation – we believe automation is globally sourced and does not change in cost between countries although we are still checking on this assumption.
  4. Building – in the past we assumed that building costs were the same by country believing the major components were globally sourced. In our expert interviews we found there is a significant difference in cost per country. Revisiting fab construction costs we have in our databases also found differences after accounting for product types. Our latest Strategic Cost and Price Model fully accounts for these differences.
  5. Building Systems – as with the building we assumed building systems were globally sourced and the cost didn’t vary by country, but this only partially true. Our latest Strategic Cost and Price Model fully accounts for these differences.
  6. Capital Incentives – if a company receives government grants to help pay for the investments to build a wafer fab, they will impact the actual capital outlay for the company building the Fab. In the past we have not accounted for this, we now allow capital incentives to be entered into the model.

Our models all calculate the capital investment by fab using a detailed bottoms-up calculation. The equipment, equipment installs, and automation are then depreciated over five years, the building systems over ten years and the building over fifteen years. We use these default values because most companies use these lifetimes for reporting purpose. There are lifetimes by country differences for tax purposes, but taxes and reporting values are typically calculated separately. There are some companies that don’t use five years for equipment but to enable consistent comparison between fabs we use five years as a default, although the ability to change the lifetimes is built into many of our Models.

Equipment Maintenance – equipment maintenance costs include consumable items, repair parts and service contracts. The technicians and engineers that maintain equipment at a company are accounted for in the Indirect Labor Cost described below.

In our Strategic Cost and Price Model the country differences are accounted for as follows:

  1. Consumables – we continue to believe this is the same by country but there are company to company differences. For example, an etcher has quartz rings in the etch chamber that some companies source from the Original Equipment Manufacturers and other companies may source in the secondary market at lower cost.
  2. Repair Parts – repair parts are distinct from consumables in that they aren’t expected to normally wear out during operation. We believe these are globally sourced and don’t vary in cost by country.
  3. Service Contracts – we believe there is some difference in service contract costs due to labor rate differences.

Our latest Strategic Cost and Price Model fully accounts for these differences.

Indirect Labor (IDL) – IDL is made up of engineers, technicians, supervisors and managers, our Models have engineer salaries by country for twenty-four countries by year and ratios are used to calculate the technician, supervisor, and manager salaries. Difference in engineer salaries vary by 12x between the lowest cost and highest cost countries. For each process/fab being modeled we look at the IDL hours required for the process and break out the IDL hours between the four IDL categories. We believe all our Models correctly reflect country to country differences currently. As with DL costs, IDL costs have less impact on wafer cost than you might expect but are more significant than DL costs.

Facilities – we break out facilities into Ultrapure Water, Water and Sewer, Electric, Natural Gas, Communications, Building Systems Maintenance, Facility Occupancy, and Insurance. The main costs are Electric, Natural Gas, Building Systems Maintenance, and Insurance. Our Models all account for Electric and natural gas rates by country for twenty-four countries. Electrical rates vary by 2.8x by country and natural gas by 7.6x by country and both are fully accounted for in the models. Facility system maintenance and facility occupancy also vary by country. Our latest Strategic Cost and Price Model fully accounts for these differences.

Consumables – all our Models calculate consumables in varying degrees of detail. We believe materials are sourced globally and do not vary in price by country. There are some country-to-country tariff differences but the implementation of this is so complex and constantly changing that we do not model. It. We do not believe the impact is significant.

Profit and Loss – Continued

 Line 3 – Gross Margin

Gross Margin isn’t part of a COGS discussion but many of our customers buy wafers from foundries. Foundry wafer prices are Wafer Cost + Foundry Margin and we have put significant effort into providing Foundry Margin guidance in our models. Foundry Margins in our Models vary company to company and within a company by year and quarter, purchasing volume and process node. They are not country dependent.

Line 4 – Period Expenses

 Not relevant to a wafer cost discussion

Line 5 Operating Income

Not relevant to a wafer cost discussion

There are two other places in the P&L where we may see country-to-country impact.

Line 6 Income Before Taxes

if a government offers a company low-cost loan this would reduce interest expenses in the interest line. In my opinion low-cost loans are incentives.

Line 7 Net Income

Tax – there are two pieces to the tax line, one is country-to-country tax rate differences and the other is preferential tax rates. In my opinion tax rate differences are a structural difference whereas a preferential tax rate is an incentive. For example, the corporate tax rate in the US is 25.8% and in Taiwan is 20%. These tax rates are normally applied to Income Before Taxes.

In summary we see country to country operating cost differences and our current release of our Strategic Cost and Price Model models these differences accurately and in detail.

There is also country to country tax rate differences that we don’t model because they are below the COGS line.

Finally, there are incentives, we see these as having three parts:

  1. Capital grants that would reduce capital cost and therefore depreciation in COGS.
  2. Low-rate loans that would impact interest expenses.
  3. Tax incentives, investment, R&D and other tax reductions.

TSMC Arizona Fab

Having reviewed all the elements of wafer cost difference we can now investigate how TSMC’s cost in Arizona will match up to their cost in Taiwan.

TSMC currently produces 5nm wafers in Fab 18 – phases 1, 2, and 3 in Taiwan. We believe each phase is current running 40,000 wafer per month (wpm) with plans to ramp to 80,000 wpm per phase over the next two years. In contrast the Arizona fab is planned to produce 20,000 wpm (at least initially). This will lead to three differences in costs:

  1. Country to country operating cost difference – after accounting for all the operating cost differences, we now find a 7% increase in cost to operate in Arizona versus Taiwan. We find a higher difference than we did previously due to now including some factors we had previously missed. Having reviewed a P&L line by line and consulting with a wide range of experts we do not believe there are any missing parts to this analysis. An interesting note here is direct labor cost in the US are over 3x the rate in Taiwan, but they have only minimal impact because in Taiwan direct labor is only 0.1% of the wafer cost and even tripling or quadrupling the labor rate it is still less than 1% of the wafer cost. Utility costs are the other hand are lower in the US.
  2. Fab size differences – accounting for a 20,000 wpm fab in the US versus 80,000 wpm in Taiwan, plus the efficiency of clustering multiple fabs together in Taiwan adds 10% to the country-to-country difference found in 1. For a total 17% difference. We want to highlight that the 10% additional cost is due to TSMC’s decision to build a small fab in the US. We expect the initial Arizona cleanroom to have room to ramp up to more than 20,000 wpm and the site to have room for additional cleanrooms. Over time if TSMC ramps up and expands the site the 10% difference can be reduced or eliminated.
  3. Incentives – to the best of my knowledge Taiwan does not offer direct capital grants. To the best of my knowledge Taiwan does not offer low-cost loans. In the past Taiwan offered tax rebates for capital investment in fabs but my understand is this program has ended. There are R&D tax rebates available, and Taiwan has a lower corporate tax rate than the US (although this isn’t an “incentive” in my view). To investigate the tax advantage for TSMC in Taiwan versus the US I have compared TSMC’s effective tax rate over the last three years to Intel’s effective tax rate in the last three years. Surprisingly they aren’t that different, now I know there is a lot of complex financial engineering in Taxes, but it is the best comparison I can find. TSMC ‘s tax rate for 2018, 2019 and 2020 is 11.7%, 11.4% and 11.4% respectively. Over the same period Intel’s tax rate was 9.7% (one-time benefits) in 2018, 12.5%, in 2019, and 16.7% (NAND Sale) in 2020. So over three years TSMC paid 11.5% and Intel paid 13.1% as a tax rate which isn’t that different.

Conclusion

The bottom line to all this is the cost for TSMC to make wafers in the US is only 7% higher than Taiwan if they built the same size fab complex in the US as what they have in Taiwan. Because they are building a smaller Fab complex the cost will be 17% higher but that is due to TSMC’s decision to build a smaller fab, at least initially.

I do want to point out this doesn’t mean the US is not at a bigger cost disadvantage versus any other country. India has reportedly discussed providing 50% of the cost of a fab as part of an attempt to get Taiwanese companies to set up a fab in India. At least in the past the national and regional governments in China have offered large incentives. Israel has also provided significant incentives to Intel in the past. But under current conditions a US fab is only 7% more expensive than a fab in Taiwan if all factors other than the location are the same.

Also Read:

Intel Accelerated

VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials

VLSI Technology Symposium – Imec Forksheet