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BDA TSMC Theater Presentation

BDA TSMC Theater Presentation
by Daniel Nenni on 06-12-2012 at 5:00 pm
Categories: EDA, Foundries, TSMC

I caught the Berkeley Design Automation presentation in the TSMC Theater, where Simon Young (BDA’s director of product marketing) described the Analog FastSPICE (AFS) nanometer circuit verification platform, built on their foundation of very fast, very accurate, high capacity circuit simulation.

BDA claims the AFS platform offers the fastest and most accurate circuit simulation, with single-core performance 5x to 10x faster than other foundry-certified simulators, and up to a further 4x faster with multithreading. AFS is consistently endorsed by designers of data converters, PLLs and DLLs, SerDes and other high-speed I/O, RFCMOS, and CMOS image sensors.

AFS is certified on several TSMC process technologies from 65nm down to 20nm through the TSMC SPICE-Qualification Program. In addition, BDA and TSMC have for several years collaborated on the device noise sub-flow for the TSMC analog and mixed-signal reference flow. Together the two companies qualified AFS’s full-spectrum transient noise analysis for this flow. A great many transient simulations are needed for this qualification process, including MOS white and flicker noise sources. Very close correlation to silicon is necessary for certification to be granted. These steps are repeated for a variety of complex mixed-signal IPs, including ADCs and PLLs.

Two recent customer example circuits illustrate the value of this qualification. Firstly, a closed-loop 14GHz PLL circuit from Analog Bits, designed for 100GbE applications, passed through performance signoff with AFS transient noise. Correlation between transient noise simulation and silicon was within 2dB. A second circuit, a delta-sigma ADC from Qualcomm, exhibited a 25dB increase in SNDR when AFS simulations including transient noise were run. Correlation between transient noise simulation and silicon was within 1.5dB. Many other examples were share last fall, at BDA’s nanometer Circuit Verification Forum.

AFS’s numerical noise floor is well below 160dB. Nanometer circuit designers demanding high dynamic range and high noise bandwidth value this accuracy. SPICE simulators achieve 60dB dynamic range with default settings, so tightening tolerances is required for trustworthy performance signoff of innovative architectures on nanometer process technologies.

Contrary to digital fastSPICE simulators that use table lookup models and an event-driven algorithm to deliver speed and capacity at the cost of accuracy, Simon compared the AFS Circuit Simulator to foundry-endorsed “sign-off” SPICE simulators. AFS solves the device analytical equations and the full matrix every simulation time-step. The difference is that tightening simulation tolerances doesn’t cause AFS to slow-down in the same way that other simulators do. And AFS always converges on a DC solution and runs transient simulation quickly, even for circuits above 10M elements.

For all this accuracy and speed, some designers want to run fast functional verification and don’t need nanometer SPICE accurate results. AFS offers a combination of user-selectable options to relax tolerances, simplify models, and simplify netlists (with RC reduction, for example). With these options set, AFS performance increases by another 4x to 5x.

Clearly, for nanometer accurate circuit simulation, 5x to 10x — or more — faster than alternatives, for large and complex circuits of 10M elements, foundry-certified AFS offers a great solution.

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Industry Standard FinFET versus Intel Tri-Gate!

Industry Standard FinFET versus Intel Tri-Gate!
by Daniel Nenni on 06-03-2012 at 6:00 pm
Categories: Foundries, Intel Foundry, TSMC
10 Comments

Ever since the “Intel Reinvents Transistors Using New 3-D Structure” PR campaign I have been at odds with them. As technologists, I have nothing but respect for Intel. The Intel PR department, however, quite frankly, is evil. Correct me if I’m wrong here but Intel did not “reinvent” the transistor. Nor did they come up with the name Tri-Gate. If not for prior art, Intel would certainly have trademarked it, my opinion.

As I previously wrote, other than the unique profile chosen by Intel for their Tri-Gate implementation, there really is no key technical distinction between Tri-Gate and the industry standard term FinFET. According to Dan Hutcheson, CEO of VLSI Research, who follows Intel rather closely:

The reason why Intel calls its FinFET a Tri-Gate is that it is a subspecies of the technology. The original FinFET was a bigate. When Intel first developed theirs (way back in the last decade) out of respect for Chenming they named it a Tri-Gate, so as not to draw from UCB’s work. Out of respect? What does that say about the rest of the industry drawing from Chenming’s work that is using the FinFET moniker? Plus, Dan says, the real importance of the Tri-Gate is not so much the third gate, but the fact that it is so much easier to manufacture than a bi-gate. That was the real contribution of Intel.

According to my sources this is not entirely true. The original paper(s) from Chenming’s group at UC-B did propose a “dual gate” (possibly even independent) structure. In the original proposal, the top surface of the FinFET would receive a thicker dielectric than the sidewalls, and not contribute to the device current. If the fin was covered by a single, continuous gate material, that would be a “dual gate”. If the gate material was etched and the sidewalls were covered by separate gates, that would be an “independent dual gate”. (Offering two independent input signals to a FinFET device provides some unique power/performance tradeoff optimizations not available with a single input signal to the transistor.)

However, lots of researchers pursuing FinFET fabrication realized that the “dual” gate (especially the dual-independent option) would be very difficult to fabricate with high yield in production. As a result, technical papers began to emerge with the triple-gate option, where the (thin) gate dielectric was also present on top of the fin, in addition to the sidewalls. The third gate surface on top of the fin is not as effective as the gate on the two sidewalls, as your note indicates.

Here’s an example of some of the triple-gate research:

Burenkov and Lorenz, “Corner effect in double and triple gate FinFET’s”, 33rd Conference on European Solid-State Device Research, 2003, p.135-138.

So, Intel was among many to pursue triple gate FinFET fabrication. And, they were certainly not the only research team to use the term “tri-gate” 10+ years ago:

Breed and Roenker, “Dual-gate and Tri-gate FinFET’s: Simulation and Design”, International Semiconductor Device Research Symposium, 2003, p. 150-151.

So, the use of the term is not really in deference to Chenming or UC-B — it’s a “de facto” standard term that the industry has used for the FinFET fabrication option that Intel has chosen.

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Intel’s Tri-Gate May Have Moore Problems Than You Think!

Intel’s Tri-Gate May Have Moore Problems Than You Think!
by Daniel Nenni on 05-29-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC


Clever title but it’s not mine. Piper Jaffray Analysts Auguste Richard and Jennifer Baxter released a report last week which echoed the concerns of others, including myself. The concerns reported are with the 22nm process and not the chipsets themselves. To me this is all part of ramping a leading edge process but the concerns are real and should be discussed.

Continue reading “Intel’s Tri-Gate May Have Moore Problems Than You Think!”

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Semiconductor Ecosystem Keynotes: ARM 2012

Semiconductor Ecosystem Keynotes: ARM 2012
by Daniel Nenni on 05-17-2012 at 5:00 pm
Categories: Arm, Cadence, EDA, ESD Alliance, GlobalFoundries, IP, Semiconductor Services, Synopsys, TSMC
2 Comments

Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…

First up was Jim Feldham, President of Semico Research with some interesting industry forecast slides. Semiconductor revenue grew 1.3% in 2011 and is predicted to grow 9% in 2012, very believable, even with 28nm wafer allocation. Tablets (+46%) and Smartphones (+34%) lead the way with the SoC market reaching $85B. I agree with this assessment 100%.

Second up was Warren East, ARM CEO. I like Warren, he is a humble man (like me) and has the traditional British dry sense of humor (unlike me). Warren’s presentations pack the most content you will see from a semiconductor CEO. Since ARM owns 99.99% (exaggeration) of the mobile business their customer surveys are very relevant. Here are some interesting takeaways from Warren’s slides:

  • 5B+ People Connected
  • $10 Mobile Phones
  • Mobile Devices Outsell PCs
  • Always On, Always Connected

Warren didn’t mention “He who must not be named” (Intel) but clearly this is a clean shot at them:

  • Fabless Model Lowers Costs
  • IP is Key: 100+ Blocks Per Chip
  • $200M Cost for 14nm SoC
  • Design Costs = 52.8% Software + 47.2% Hardware
  • Standards Reduce Costs

Taking a “systems” view:

  • A vibrant ecosystem is maintained through collaboration and aligned investments
  • Tweaks to current models will not solve big challenges or drive significant growth
  • Boundaries will need to shift and change, enabling broader IP and services that spread development costs across the chip ecosystem

Bottom line: It’s all about the ecosystem. Linaro is one example as I blogged in Intel Versus ARM (Linaro).

The SoC Design community is dedicated to design engineers developing highly integrated system-on-chip solutions with ARM technology. This site addresses every phase of SoC design, from architecture selection through front end design and back end implementation and manufacturing. Learn more about best practices for designing advanced SoCs based on ARM Cortex processors, Artisan physical IP, CoreLink system IP and ARM Connected Community IP, tools and services.

ARM has a landing page on SemiWiki now which you can find HERE, ARM related blogs are organized there. The theme you will notice is ecosystem and SoC. SemiWiki blogger Don Dingee has a series of blogs on Smart Mobile SoCs including NVIDIA, Apple, Samsung, TI, and Qualcomm. He even did one on Intel: Smart Mobile SoCs: Intel. Don will go to China for the next one so stay tuned!

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TSMC Tops Intel, Samsung in Capacity!

TSMC Tops Intel, Samsung in Capacity!
by Daniel Nenni on 05-13-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC
8 Comments

While I was marlin fishing in Hawaii last week I missed some interesting comments from TSMC executives at the Technology Symposium in Taiwan, a much different show than the one here in San Jose I’m told. It is good to see TSMC setting the record straight and taking a little credit for what they have accomplished! I’m sorry I missed it but I know quite a few people who didn’t and they were quite impressed.

Y.P. Chin, TSMC Vice President for operations and product development (Y.P. joined TSMC when it was founded in 1987):

Citing data from SEMI, TSMC’s capacity for logic chips was 1.5 times greater than Intel and 2 times greater than Samsung in 2011.

Interesting perspective. If you look inside your smartphone or tablet you will see both logic (brains) and DRAM (memory) chips. TSMC does the brains, Samsung does mostly memory, Intel does the big fat brain in your PC and laptop (my wife edits my blogs so this is for her).

Jason Chen, TSMC’s Senior Vice President of Worldwide Sales and Marketing (Prior to joining TSMC in 2005, Jason worked at Intel for 14+ years):

Smartphones have beat PCs in shipments since 2010. In 2012, shipments of smartphones will beat PCs by 50%. Tablets join smartphones to make mobile computing an even bigger market. Smartphones have emerged as the primary tools for internet access with even more features fit inside in the future. Online payment for example will become a standard smartphone feature.

I never thought I would give up my laptop but my iPhone 4s and iPad2 see much more action than I would have ever imagined. My wife and kids (ages 16, 18, 22, and 24) will tell you the same, absolutely. I even used my iPhone projected boarding pass to get to and from Hawaii avoiding check-in lines, very cool!

That is why TSMC is leading off 20nm with a process optimized for mobile and Intel will need to optimize their 22nm process for mobile before mainstream customers take their foundry claims seriously.

That is also why TSMC is increasing CAPEX and R&D spending to record rates this year, to capture as much mobile demand as possible. One thing you have to remember about the foundry business is that wafer price is everything, especially to the mobile market. Today TSMC is the only foundry shipping production 28nm silicon which means they have a big lead on the manufacturing yield/cost curve. Even when second source 28nm silicon hits the market it will be at a higher cost/lower margin. TSMC will also be the first with 20nm silicon (my opinion) so lather, rinse, repeat…

A question I have is: How much longer will TSMC stock (TSM) continue to trade for under $16? Anyone? Given the success of 28nm, I think you will be able to measure that in months versus years (my opinion).

Disclaimer: I do not partake in the financial markets so do not buy this or any other stock based on my comments. Seriously, you would be better off consulting your neighbor’s pet.

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Intel Foundry All Hat No Cattle?

Intel Foundry All Hat No Cattle?
by Daniel Nenni on 05-12-2012 at 12:19 am
Categories: Arm, EDA, Events, Intel Foundry, IP, TSMC
1 Comment

If you look real close at the #49 DAC floor plan you will see the tiny Intel booth dwarfed by those of TSMC, GlobalFoundries, Samsung, and ARM. The number one semiconductor company in the world does not have the budget for the cornerstone conference of the semiconductor ecosystem? Oh my…… Intel has a big foundry hat and no cattle this year.

Now in its 49th year (this will be my 29[SUP]th[/SUP]), the Design Automation Conference features a wide array of technical presentations, tutorials, and workshops, as well as more than 200 of the leading semiconductor ecosystem partners in a colorful, well-attended trade show that attracts thousands of semiconductor professionals from around the world.

This year, industry luminaries from ARM, Inc., IBM Corp., Intel Corp. and the National Tsing Hua University will give the three keynote addresses. DAC 2012 will be held at my absolute favorite venue, other than Las Vegas, the Moscone Center in San Francisco, California, from June 3-7, 2012.


“In assembling the 49th DAC series of distinguished keynotes speakers, I am excited to announce that DAC is covering all bases, providing refreshing viewpoints for systems designers, IC designers and EDA software professionals,” said Patrick Groeneveld, General Chair of the 49th DAC.

“Tuesday kicks off with ARM’s Mike Muller, who will share his vision for a future of embedded computing systems. Given that ARM’s processors power most smartphones, this will show the way for computing in the future.”

“On Wednesday, Joshua Friedrich and Brad Heaney will outline the design practices for high-performance microprocessors. This unique dual-keynote provides a look in the kitchen of leading microprocessor companies designing the world’s most advanced chips,” Patrick enthusiastically continued.

“Finally, the Thursday keynote by Kaufman Award winner Dave Liu addresses the algorithmic revolution behind EDA. Prof. Liu’s contributions and insights have enabled the remarkable design automation revolution that actually powers today’s trillion-transistor devices.”

Keynote Schedule:
All keynotes will be held in rooms 102/103.

Tuesday, June 5, 2012 from 8:30am to 9:30am
Scaling for 2020 solutions
Mike Muller, CTO, ARM Inc., Cambridge, U.K.

Comparing the original ARM design of 1985 to those of today’s latest microprocessors, Mike will look at how far design has come and what EDA has contributed to enabling these advances in systems, hardware, operating systems, and applications as well as how business models have evolved over 25 years. He will then speculate on the needs for scaling designs into solutions for 2020 from tiny embedded sensors through to cloud-based servers that together enable the “Internet of things.” Mike will look at the major challenges that need to be addressed to design and manufacture these systems and propose some solutions.

Wednesday, June 6, 2012 from 10:45am to 11:45am
Designing High Performance Systems-on-Chip
Joshua Friedrich, Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. Brad Heaney, Intel Architecture Group Project Manager, Intel Corp., Folsom, CA.

Experience state-of-the art design through the eyes of these two experts. Joshua Friedrich will talk about POWER processor design and methodology directions and Brad Heaney will discuss designing the latest Intel architecture multi-CPU and GPU. In this unique dual-keynote, the speakers will cover key challenges, engineering decisions and design methodologies to achieve top performance and turn-around time. The presentations describe where EDA meets practice under the most advanced nodes.

Thursday, June 7, 2012 from 11:00am to 12:00pm
My First Design Automation Conference – 1982
C. L. (Dave) Liu of Tsing Hua University and also the recipient of the 2012 Phil Kaufman award.

Dave tells us: “It was June 1982 that I had my first technical paper in the EDA area presented at the 19th Design Automation Conference. It was exactly 20 years after I completed my doctoral study and exactly 30 years ago from today. I would like to share with the audience how my prior educational experience prepared me to enter the EDA field and how my EDA experience prepared me for the other aspects of my professional life.”

I hope to see you all there!

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TSMC 20nm Challenges!

TSMC 20nm Challenges!
by Daniel Nenni on 05-06-2012 at 7:00 pm
Categories: EDA, Foundries, TSMC
4 Comments

Now that the 28nm challenges are dead
It is time to look ahead
The tabloid pundits may not agree
But Moore’s law again you will see
The semiconductor ecosystem is humming
(2X gate density -20%+ performance-20%+ power savings)
The 20nm design starts are coming!

Okay, I’m really bad at poetry. Gambling however, I do pretty well. Las Vegas is my favorite destination, a mere 6 hour Porsche drive from Danville. It’s not just the math of gambling that’s intriguing, it’s also how you read a person, a play, or situation. I literally won all of my bets on 28nm and 20nm looks like another great gambling opportunity. I have two more kids to get through college so put your money where your mouth is.

Here is why the 20nm challenges will be vanquished in record time: GREED, simple as that! As I mentioned before, the semiconductor ecosystem consists of a very large crowd of very smart people with very big egos who really like making money (me for example). Whomever solves the 20nm design and manufacturing puzzles first not only gets fame, they also get fortune. Talk about motivation. And who doesn’t like solving puzzles?

20nm blogs-white papers-webinars are in play
20nm test chips arriving every day
40nm we learned how to yield
28nm we yearned for capacity
20nm will be an even bigger payday!

Better? Intel has done us all a really big favor. They are shooting their mouth off, motivating the masses, because who in their right mind would NOT want to prove Intel wrong? Especially if you can make money while doing it. Sign me up!

Here is the biggest bet: What will the TSMC 20nm ramp look like?

Remember, even though the tabloid press had 28nm “not yielding at all” and “shut down for weeks” in Q1 2012, the ramp thus far has beat expectations. The questions are:

[LIST=1]

  • Will 20nm be on par with 28nm?
  • When will the 20nm ramp officially start?
  • How far behind the Intel 22nm SoC mobile version will it be?


    According to the SemiWiki crowd, Apple will be at TSMC 20nm:

    Who will Apple partner with at 20nm?

    [LIST=1]

  • TSMC 38.04%
  • Intel 25.00%
  • Neither (stay at Samsung) 19.57%
  • Both 17.39%

    So you might want to factor that extra motivation into your gambling equation.

    My trip this week was off a bit due to the national Taiwan holiday on Tuesday so here I sit in the EVA Executive Lounge on a sunny Saturday afternoon.

    Don’t feel bad for me there’s an open bar
    Don’t feel bad for me I have a beautiful car
    Don’t feel bad for me this week I’m fishing afar

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    IC design at 20nm with TSMC and Synopsys

    IC design at 20nm with TSMC and Synopsys
    by Daniel Payne on 05-02-2012 at 10:25 am
    Categories: EDA, Foundries, Synopsys, TSMC

    willychen80x95

    While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.
    Continue reading “IC design at 20nm with TSMC and Synopsys”