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BDA TSMC Theater Presentation

BDA TSMC Theater Presentation
by Daniel Nenni on 06-12-2012 at 5:00 pm

I caught the Berkeley Design Automation presentation in the TSMC Theater, where Simon Young (BDA’s director of product marketing) described the Analog FastSPICE (AFS) nanometer circuit verification platform, built on their foundation of very fast, very accurate, high capacity circuit simulation.

BDA claims the AFS platform offers the fastest and most accurate circuit simulation, with single-core performance 5x to 10x faster than other foundry-certified simulators, and up to a further 4x faster with multithreading. AFS is consistently endorsed by designers of data converters, PLLs and DLLs, SerDes and other high-speed I/O, RFCMOS, and CMOS image sensors.

 AFS is certified on several TSMC process technologies from 65nm down to 20nm through the TSMC SPICE-Qualification Program. In addition, BDA and TSMC have for several years collaborated on the device noise sub-flow for the TSMC analog and mixed-signal reference flow. Together the two companies qualified AFS’s full-spectrum transient noise analysis for this flow. A great many transient simulations are needed for this qualification process, including MOS white and flicker noise sources. Very close correlation to silicon is necessary for certification to be granted. These steps are repeated for a variety of complex mixed-signal IPs, including ADCs and PLLs.

Two recent customer example circuits illustrate the value of this qualification. Firstly, a closed-loop 14GHz PLL circuit from Analog Bits, designed for 100GbE applications, passed through performance signoff with AFS transient noise. Correlation between transient noise simulation and silicon was within 2dB. A second circuit, a delta-sigma ADC from Qualcomm, exhibited a 25dB increase in SNDR when AFS simulations including transient noise were run. Correlation between transient noise simulation and silicon was within 1.5dB. Many other examples were share last fall, at BDA’s nanometer Circuit Verification Forum.

AFS’s numerical noise floor is well below 160dB. Nanometer circuit designers demanding high dynamic range and high noise bandwidth value this accuracy. SPICE simulators achieve 60dB dynamic range with default settings, so tightening tolerances is required for trustworthy performance signoff of innovative architectures on nanometer process technologies.

 Contrary to digital fastSPICE simulators that use table lookup models and an event-driven algorithm to deliver speed and capacity at the cost of accuracy, Simon compared the AFS Circuit Simulator to foundry-endorsed “sign-off” SPICE simulators. AFS solves the device analytical equations and the full matrix every simulation time-step. The difference is that tightening simulation tolerances doesn’t cause AFS to slow-down in the same way that other simulators do. And AFS always converges on a DC solution and runs transient simulation quickly, even for circuits above 10M elements.

For all this accuracy and speed, some designers want to run fast functional verification and don’t need nanometer SPICE accurate results. AFS offers a combination of user-selectable options to relax tolerances, simplify models, and simplify netlists (with RC reduction, for example). With these options set, AFS performance increases by another 4x to 5x.

Clearly, for nanometer accurate circuit simulation, 5x to 10x — or more — faster than alternatives, for large and complex circuits of 10M elements, foundry-certified AFS offers a great solution.

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