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TSMC Update 2012!

TSMC Update 2012!
by Daniel Nenni on 05-31-2012 at 7:15 pm

 TSMC has had an interesting year thus far. 28nm is ramped and will dominate the mobile market for years to come. 20nm is in development with tape outs scheduled for the end of this year. FinFETS are coming making it a very exciting time in the semiconductor ecosystem.

More recently, Renesas is the latest IDM to go fab-lite working with TSMC at 40nm and below. Clearly the demise of the fabless business model is greatly exaggerated. Clearly 28nm was harder than expected and 20nm will thin the IDM herd even more.

TSMC has a SemiWiki landing page HERE. As they say, you can tell a lot about a company by their DAC plan. While Intel and the Orcs are fantasizing the fall of the fabless business model, TSMC and their legions of EDA, IP, and fabless semiconductor partners march on towards the Fires of Mooredor. Get it? Moore’s Law? Fires of Mordor? My wife laughed out loud so the Hobbit reference plays..

TSMC Theater Presentation Schedule

[TABLE] cellpadding=”4″ style=”width: 100%”
|-
| align=”center” | Time
| align=”center” style=”width: 30%” | Monday 6/4
| align=”center” style=”width: 30%” | Tuesday 6/5
| align=”center” style=”width: 30%” | Wednesday 6/6
|-
| align=”center” | 9:30am
| align=”center” | Analog Bits
| align=”center” | Solido Design Automation
| align=”center” | Sigrity
|-
| align=”center” | 9:45am
| align=”center” | MunEDA
| align=”center” | Mentor Graphics
| align=”center” | Lorentz Solution
|-
| align=”center” | 10:00am
| align=”center” | Ansys/Apache
| align=”center” | ARM
| align=”center” | SpringSoft
|-
| align=”center” | 10:15am
| align=”center” | Dolphin Integration
| align=”center” | Integrand Software
| align=”center” | eSilicon
|-
| align=”center” | 10:30am
| align=”center” | Helic
| align=”center” | Atrenta
| align=”center” | Berkeley Design Automation
|-
| align=”center” | 10:45am
| colspan=”3″ align=”center” | Break
|-
| align=”center” | 11:00am
| align=”center” | iRoC Technologies
| align=”center” | Synopsys
| align=”center” | Cadence Design Systems
|-
| align=”center” | 11:15am
| align=”center” | True Circuits
| align=”center” | GUC
| align=”center” | Uniquify
|-
| align=”center” | 11:30am
| align=”center” | ATopTech
| align=”center” | Cadence Design Systems
| align=”center” | True Circuits
|-
| align=”center” | 11:45am
| align=”center” | GUC
| align=”center” | Helic
| align=”center” | Dorado Design Automation
|-
| align=”center” | 12:00am
| align=”center” | TSMC
| align=”center” | TSMC
| align=”center” | TSMC
|-
| align=”center” | 12:15am
| colspan=”3″ align=”center” | Raffle
|-
| align=”center” | 12:30am
| colspan=”3″ align=”center” | Break
|-
| align=”center” | 1:15pm
| align=”center” | Synopsys
| align=”center” | Lorentz Solution
| align=”center” | Analog Bits
|-
| align=”center” | 1:30pm
| align=”center” | Integrand Software
| align=”center” | Berkeley Design Automation
| align=”center” | Helic
|-
| align=”center” | 1:45pm
| align=”center” | Atrenta
| align=”center” | SpringSoft
| align=”center” | Ansys/Apache
|-
| align=”center” | 2:00pm
| align=”center” | Mentor Graphics
| align=”center” | Dorado Design Automation
| align=”center” | ARM
|-
| align=”center” | 2:15pm
| colspan=”3″ align=”center” | Break
|-
| align=”center” | 2:30pm
| align=”center” | Solido Design Automation
| align=”center” | Sigrity
| align=”center” | iRoC Technologies
|-
| align=”center” | 2:45pm
| align=”center” | Uniquify
| align=”center” | MunEDA
| align=”center” | ATopTech
|-
| align=”center” | 3:00pm
| align=”center” | Cadence Design Systems
| align=”center” | Uniquify
| align=”center” | Mentor Graphics
|-
| align=”center” | 3:15pm
| align=”center” | SpringSoft
| align=”center” | Analog Bits
| align=”center” | Dolphin Integration
|-
| align=”center” | 3:30pm
| align=”center” | Lorentz Solution
| align=”center” | Ansys/Apache
| align=”center” | Solido Design Automation
|-
| align=”center” | 3:45pm
| colspan=”3″ align=”center” | Break
|-
| align=”center” | 4:00pm
| align=”center” | Berkeley Design Automation
| align=”center” | True Circuits
| align=”center” | Synopsys
|-
| align=”center” | 4:15pm
| align=”center” | Sigrity
| align=”center” | eSilicon
| align=”center” | MunEDA
|-
| align=”center” | 4:30pm
| align=”center” | ARM
| align=”center” | iRoC Technologies
| align=”center” | GUC
|-
| align=”center” | 4:45pm
| align=”center” | Dorado Design Automation
| align=”center” | ATopTech
| align=”center” | Atrenta
|-
| align=”center” | 5:00pm
| align=”center” | TSMC
| align=”center” | Dolphin Integration
| align=”center” | Integrand Software
|-
| align=”center” | 5:15pm
| colspan=”3″ align=”center” | Raffle
|-

TSMC Activities Schedule

[TABLE] cellpadding=”4″ style=”width: 100%”
|-
| align=”center” | Sponsored by
| align=”center” style=”width: 15%” | Activity
| align=”center” style=”width: 30%” | Title
| align=”center” style=”width: 15%” | Date
| align=”center” style=”width: 15%” | Time
| align=”center” style=”width: 12%” | Location
|-
| align=”center” | DAC
| align=”center” | Workshop
| align=”center” | CMOS Design at 60GHx and Beyond: Capabilites & Challenges
| align=”center” | 6/3 Sunday
| align=”center” | 8:30AM – 12:30PM
| align=”center” | Room 305
|-
| align=”center” | DAC
| align=”center” | Tutorial #2
| align=”center” | Enough Talk!
Practical Approaches to 3-D IC – TSV/Silicon Interposer and Wide IO
| align=”center” | 6/4 Monday
| align=”center” | 8:30AM – 10:30AM
11:30AM – 1:30PM
3:30PM – 5:30PM
| align=”center” | Room 302
|-
| align=”center” | DAC
| align=”center” | Tutorial #5
| align=”center” | Analog and Mixed-Signal Design at Advanced Process Node
| align=”center” | 6/4 Monday
| align=”center” | 8:30AM – 10:30AM
11:30AM – 1:30PM
3:30PM – 5:30PM
| align=”center” | Room 306
|-
| align=”center” | DAC
| align=”center” | User Track – Poster Presentation #2U.25
| align=”center” | LDE-Aware Design Solution for Advanced Technologies
| align=”center” | 6/5 Tuesday
| align=”center” | 12:30PM – 1:30PM
| align=”center” | Room 105
(Exhibit Floor)
|-
| align=”center” | DAC
| align=”center” | Technical Panel (Session 37)
| align=”center” | Is 3D Ready for the Next Level?
| align=”center” | 6/7 Thursday
| align=”center” | 9:00AM – 10:30AM
| align=”center” | Room 305
|-
| align=”center” | ARM
| align=”center” | Booth Presentation
| align=”center” | Advanced Technology, Process/Processor Co-Optimization
| align=”center” | 6/4 Monday
| align=”center” | 11:30AM – 12:00PM
| align=”center” | ARM Booth
# 802/1414
|-
| rowspan=”2″ align=”center” | Cadence
| rowspan=”2″ align=”center” | EDA 360 Theatre
| align=”center” | N20 Certification
| align=”center” | 6/4 Monday
| align=”center” | 11:30AM – 12:00PM
| rowspan=”2″ align=”center” | Cadence Booth
# 1930
|-
| align=”center” | 3DIC Program
| align=”center” | 6/6 Wednesday
| align=”center” | 9:30AM-10:00AM
|-
| align=”center” | Chip Estimate
| align=”center” | IP Talks (Booth Presentation)
| align=”center” | TSMC OIP IP alliance
| align=”center” | 6/4 Monday
| align=”center” | 2:30PM – 3:00PM
| align=”center” | ChipEstimate Booth
# 1202
|-
| align=”center” | Synopsys
| align=”center” | Conversation Central Interview
| align=”center” | IP Quality – It’s Imperative!
| align=”center” | 6/6 Wednesday
| align=”center” | 2:45PM – 3:30PM
| align=”center” | Synopsys Booth
# 1730
|-
| align=”center” | Mentor
| align=”center” | Booth Presentation
| align=”center” | Advanced Fill Techniques for 20nm and Below
| align=”center” | 6/6 Wednesday
| align=”center” | 2:00PM – 3:00PM
| align=”center” | Mentor Booth
# 1530
|-
| align=”center” | Atrenta
| align=”center” | DAC Monday Evening Cocktail Reception (co-sponsored by TSMC)
| align=”center” | Theme: IP Quality
| align=”center” | 6/4 Monday
| align=”center” | 6:00PM – 7:00PM
| align=”center” | Room 303 & Outdoor Terrace
|-

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