Posted on

Another Interesting Thing From TSMC!

Another Interesting Thing From TSMC!
by Daniel Nenni on 01-21-2017 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

As I mentioned in my previous post, the TSMC investor call this month was very interesting and Morris Chang was in fine form during the Q&A. As a semiconductor professional I think some of the questions are ridiculous but maybe they have value to the financial people. This one question from Randy, who I think is very astute, is SemiWiki discussion worthy:

Randy Abrams
Yes, thank you. The first question, I wanted to ask your outlook is more in line with the industry where you are guiding 5% to 10% for foundry near similar levels. Could you talk about the factors to be more inline after gaining the last few years? And can you also address the China business; we are seeing the China foundries grow faster. SMIC is growing 20% to 30%, how does TSMC combat or defend share more on the mature nodes, where they’re starting to grow faster?


(At the bottom it says SMIC is partially owned by TSMC. TSMC did get a 10% equity stake after the IP litigation which I thought TSMC had already divested. Please post a comment if you know otherwise.)

First and foremost, TSMC is being conservative as they always are and they are shielding their #1 customer which is Apple. There is no way the second half of the year will be 5% growth with Apple single sourcing 10nm from TSMC for the next iPhone and iPad. TSMC will again be in double digits (10-15% revenue growth) for 2017 as I previously stated.

This is going to be another strong year for the foundries but I do find it interesting that while the semiconductor foundry business is posting double digit gains the semiconductor industry as a whole is relatively flat… Comments?

Second, SMIC is surging on 2[SUP]nd[/SUP] source business now that they are shipping a TSMC compatible 28nm, most of which is in China. How does TSMC combat or defend the mature nodes? In China they don’t, they push the market to FinFETs. Remember, the TSMC GDS compatible market stops with FinFETs and SMIC does not expect to have 14nm until 2020 or so. Meanwhile TSMC is getting ready to release a fourth generation (12nm) FinFET process optimized for density and cost. In fact, I hope TSMC shows an updated version of the infamous Intel chip scaling graph shown below.


Remember, this graph was based on a paper done by TSMC before 16nm went into production. TSMC then released 16FF+, 16FFC, and now 12nm.

My guess is that TSMC 12nm will easily be on par with Intel 14nm in regards to chip density and superior in cost per transistor… Comments?

Unfortunately, Intel is still flogging this outdated slide. In fact, just this month at the J.P. Morgan 2017 Tech Forum, Intel Client Computing Group VP Navin Shenoy said Intel 14nm is equivalent to Samsung and TSMC 10nm so they are considering renaming their 10nm:

“I’m confident that when 10 nanometer — our 10 nanometer — comes out, and this is something that maybe we should rename it, I don’t know, we’ll think about that, but when our 10 nanometer comes out, we will have a clear density advantage, and a clear performance and power advantage versus what others in the industry have.”

Well, yes and no. Unfortunately for Intel their 10nm will come out about the same time as TSMC 7nm so no, Intel will not have a clear density advantage:

Morris Chang
I think 2017 will be pretty strong in terms of technology, it will be a pretty strong 16 or 14 FinFET year, and our market share in 16, while it’s quite high, is not as high as I would like, it’s actually in the close to 70% or 65% to 70%. Now that is not quite as high as our 28 nanometer which even now, you know, like almost 80% and now, 2017 is – I think it’s a pretty – we think will be a pretty strong year and result.

Absolutely…

Posted on

Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration

Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration
by Mitch Heins on 01-20-2017 at 12:00 pm
Categories: EDA, Siemens EDA, TSMC

I caught up with John Ferguson of Mentor Graphics this week to learn more about a recent announcement that TSMC has extended its collaboration with Mentor in the area of Fan-Out Wafer Level Processing (FOWLP).

In March of last year Mentor and TSMC announced that they were collaborating on a design and verification flow for TSMC’s InFO (integrated Fan-Out) packaging technology using Mentor’s Xpedition Enterprise and Calibre nmDRC/RVE platforms. That flow allowed designers to layout the InFO structures with Mentor’s Xpedition Package Integrator and then use Calibre nmDRC for design rule checking with cross probing back into Xpedition using Calibre RVE.

Since then, the Mentor and TSMC teams have been working closely together to enhance the flow to shorten design cycle times, minimize designer effort and ensure higher quality GDS hand-offs to improve first-time success rates. Key to the collaboration were efforts to ensure seamless assimilation of TSMC’s newest technologies whether it be single or multiple die on InFO packaging, with or without a substrate, and with or without package-on-package. To achieve this, Mentor has attacked several different areas.

Firstly, Mentor developed new Xpedition Enterprise functionality to make it easier to create InFO-specific fab-ready metal structures such as seal rings, parameterized mesh pad generation, degassing holes and additional metal for balancing metal density.

Mentor next added HyperLynx DRC technology to the flow for in-design InFO-specific manufacturing verification checks. HyperLynx DRC allows designers to find and fix DRC issues while still in the design phase reducing the number of iterations out to GDSII for DRC checking in Calibre. Final sign-off rule checking is still done with Calibre nmDRC for both die and InFO package design rule checks.

New to the flow with this release is the addition of Calibre 3DSTACK and the capability to do sign-off level layout-vs-schematic (LVS) checks for inter-die connectivity verification of the entire InFO-based package.

For IC designers this may sound trivial, but when you realize that you are possibly dealing with multiple die, each with their own CAD database, as well as data for the silicon wafer providing the InFO connectivity you start to see how messy the CAD flow can get. Also considering each die may have thousands of pins you also realize how easy it would be to get something hooked up wrong and how hard it would be to find a mistake without good LVS tools. This will be a much appreciated addition to the flow.

In December of 2016, John was interviewed for an article in Chip Scale Review in which he outlined how TSMC has worked with EDA companies like Mentor to develop EDA solutions for IC and package design with an intent to ensure that InFO designs would be fully compliant with TSMC’s packaging design rules and sign-off requirements. At that time, John mentioned that TSMC was in fact working to expand the InFO tool support into sign-off electrical analysis to enable designers to analyze the parasitic impacts from InFO and its neighboring layers. It appears this is now in place for the Mentor flow, with the addition of signal integrity checking of the InFO interconnects using signal path tracing, extraction, simulation and netlist export.

The flow also now supports integration to thermal analysis and thermally-aware post-layout simulation flows to provide early identification of potential system level heat issues. The connection to the simulation world also enables such things as multi-die reliability analysis including analysis of electromigration and IR drop.

While Fan-Out Wafer Level Processing is catching on with its promises of low cost, small form factors, and low power with high performance, the addition of a fully integrated IC and package design flow goes a long way toward making this a truly usable technology. TSMC is using its extensive expertise in generating process design kits for advanced IC processes along with their significant experience and long historic relationships with EDA players like Mentor Graphics to jump out well ahead of their OSAT (outsource assembly and test) competitors in bringing FOWLP technology into real production use.

See Also:

Posted on

IP development strategy and hockey

IP development strategy and hockey
by Tom Dillinger on 01-19-2017 at 7:00 am
Categories: Analog Bits, FinFET, IP, TSMC

eye diagrams min

One of the greatest hockey players of all time, Wayne Gretzky, provided a quote that has also been applied to the business world — “I skate to where the puck will be, not to where it has been.” It strikes me that this philosophy directly applies to IP development, as well. Engineering firms providing IP must anticipate how customer requirements will evolve, and execute a design and qualification plan well in advance of the demand curve.

I recently had the opportunity to chat with members of the engineering team at Analog Bits, providers of IP for SerDes lanes, PLL’s, memories, on-chip sensors, and I/O’s for memory (and general purpose) interfaces. They impressed upon me characteristics of current development projects that are “critical success factors” to the IP business model:

 

  • multi-protocol SerDes IP extends applicability across markets

Analog Bits has focused on development of SerDes IP to be applied for several serial interface protocols.

  • IP providers must lead in the development of (standards for) next generation high-speed SerDes data rates.

The silicon testsite plan at Analog Bits involves demonstration of 25G data rates (at leading process technology nodes).

  • Testsite silicon requires anticipating customer integration, test, and qualification requirements.

To be successful, testsite development requires a “skate to where the puck will be” strategy. Developing testsite shuttles is costly, both in NRE for silicon wafers and board-level testbench development and in engineering development resources. The IP team must invest wisely, to ensure that the resulting test measurement and qualification data will satisfy future customer requirements.

ESD qualification of I/O’s requires addressing the (evolving) CDM and HBM robustness standards demanded by end markets (e.g., JEDEC and AEC-Q100 tests).

SerDes IP on a testsite shuttle requires a test plan that demonstrates an adequate eye opening, using a topology representative of the losses that are likely to be present in the system design environment. The wrapback test specification used for IP evaluation is key — e.g., “total loss less than 22dB at 8GHz (for 16Gbps) through a loop back including 24″ of FR-4 trace”.

The SerDes physical (hard IP) implementation on the testsite also requires addressing future customer needs. The granularity of SerDes lanes, with the corresponding pad topology for signals and power, needs to satisfy a wide range of applications. The figure below illustrates the modular approach that Analog Bits has pursued.

Another example of engineering development to address customer requirements is the availability of SerDes IP cells for any die side of the customer’s SoC. At advanced process nodes, recall that an increasing number of mask layers must use unidirectional segments — e.g., device gates, lower-level metals. Unique IP cells are required for the different sites of the die. The figure below illustrates the vertical orientation SerDes cell on silicon testsites, and several examples of floorplanning testcases.

High-speed lanes are becoming more prevalent than other I/O types for performance-driven SoC’s. Demonstration of flexible, modular (hard) SerDes IP implementations with many lanes is a must.

The team at Analog Bits is focusing their engineering development and test resources on IP designs and shuttle testsites that anticipate the requirements of new markets for advanced process nodes. They are following the same approach that earned Gretzky the nickname “The Great One”.

For general information on the IP available from Analog Bits, please follow thislink.

-chipguy

Posted on

Three Interesting Things from TSMC!

Three Interesting Things from TSMC!
by Daniel Nenni on 01-13-2017 at 12:00 pm
Categories: Foundries, TSMC

First, the TSMC Museum of Innovation is now open and it’s quite impressive. Located right below Fab 12, it is definitely worth an hour of your time. Second, Morris Chang was on the investor call which made it much more interesting, especially his comments on the recent Report to the President on U.S. semiconductor leadership. Third, TSMC will be the first with EUV in production at 7nm.

The TSMC Museum of Innovation encompasses three exhibition galleries: “A World of Innovation”, “Unleashing Innovation”, and “Dr. Morris Chang, TSMC Founder”. Through interactive technology, digital content, and historical documents we will learn about the pervasiveness of ICs in our daily lives and about their continued advancement. In addition, we will learn how ICs are making our lives more fulfilling and how they are driving technology beyond our imagination. We will also learn how TSMC contributes to global IC innovation and to Taiwan’s economy.

Unfortunately, I was on a plane during the TSMC investor call but I did listen to the replay and read the transcript. As I predicted in my Double Digit Growth and 10nm for TSMC in 2016! blog, TSMC had a very good 2016 and I will again predict double digit revenue growth for 2017, absolutely.

In case you have not seen it yet, the REPORT TO THE PRESIDENT Ensuring Long – Term U.S. Leadership in Semiconductors was published last week so of course it came up in the TSMC call Q&A. The response came from Morris who countered and said TSMC has created thousands of jobs by authoring the pure-play foundry business model in 1987 (yes this is the 30[SUP]th[/SUP] year of TSMC and the fabless semiconductor industry). Morris also pointed out that this report was to Obama and not to Trump and shared an interesting anecdote about presidential reports:

I mean, we have history to guide us. In fact, just tell you an anecdote, in 2006 I met President Bush, then President of the United States, and at that time his, President Bush’s, task force, advisory task force on Iraq, had just submitted a report, basically recommended the U.S. withdrawing from Iraq. And President Bush did not adopt the recommendation. He actually adopted the contrary, which was to increase his troops in Iraq. So I mean that’s just an example that quickly came to my mind, when somebody talks about, ah, report has been written.

One thing you should know about Morris is that he is a very well read military history enthusiast and has a remarkable memory. While I’m not necessarily equating business to war there is much to be learned in regards to strategy, leadership, and human nature.

The other interesting nugget on the call is about 7nm and EUV. TSMC now has definitive plans to insert EUV into 7nm:

Mark Liu
So we think 7 nanometer is a well adopted node by all the customers and we plan for the subsequent technology to shore up the demand continuously. And we hope to use this technology – I mean the second-year technology to prepare for the EUV production experience for the full fleshed EUV technology on 5. So then our customers can have a very hopefully smooth getting to from our 7 to our 5 nanometer technology. So that is the how we maintain our technology competitiveness.

Translation: TSMC will be the first to 7nm EUV production, yes?

Posted on

Making the Move from 28nm to FinFET!

Making the Move from 28nm to FinFET!
by Daniel Nenni on 01-12-2017 at 12:00 pm
Categories: Arm, FinFET, IP, TSMC

If you click FinFET in the SemiWiki.com Latest News: navigation bar at the top of this page you will get a list of 86 blogs that have been viewed more than 600,000 times. If you go to the last blogs on the list, meaning the first blogs to be published, you will see a three part series, “Introduction to FinFET Technology” written by Tom Dillinger (ChipGuy), starting in March of 2012. That series has been viewed more than 60,000 times and is still getting traffic. Rumor has it Tom is writing a book on FinFETs to be published later this year so the series continues (in print).

Even though we have had FinFETs in production for quite some time now a significant amount of design work is still done on 28nm and above. Now that we have the cost effective TSMC 16FFC process and the even more cost effective (soon to be announced) TSMC 12nm, it’s time to get more competitive and say good-bye to planar devices, absolutely.

And ARM is going to help us do just that with their upcoming webinar:

Making the move from 28nm to 16nm FinFET: easy as POP!

Live Webinar: 9:00 am – 10:00 am PST and 5:00 – 6:00 pm PST
January 17, 2017

REGISTER HERE

The TSMC 16FFC process is a lower cost FinFET option that targets a wide range of applications. So consequently, many ARM-based partners are interested in moving from a traditional CMOS manufacturing process technology to using the FinFET process. However, designers are unsure of the challenges that may be encountered when moving to FinFET.

To facilitate meeting these new process challenges, ARM’s physical design group developed implementation solutions in both TSMC 28HPC+ and TSMC 16FFC, to both optimize and accelerate the implementation of ARM-based SoC designs. Using the latest ARM Cortex®-A73 processor as a case study, this webinar will summarize deep technical findings collected from a variety of implementation trials. We will share and discuss process differences, power grid creation challenges, floor planning differences (due to fin pitch requirements), key enhancements in clock tree synthesis, and revised signoff criteria.

If you are thinking of making the move to a FinFET technology process, this is one webinar that you do not want to miss!

And if you are designing an SoC, ARM also has a webinar for you:

Three Tips to Maximize your SoC performance

Live Webinar: 9:00 am – 10:00 am PST and 5:00 pm – 6:00 pm PST
January 24, 2017

REGISTER HERE

CPU performance is highly dependent on choices such as: processor speed, cache size, interconnect, memory speed, data ordering, data width and optimal integration of the IP blocks. In addition to focusing on the CPU, ARM also fulfills extensive system performance analysis work to ensure that the optimal configuration options are chosen by the designer.

Join this free webinar to understand more about the methodologies and analysis techniques used at ARM, plus how these link to CPU performance. This webinar will introduce some of the SoC design work carried out by ARM, with data for SoCs targeting mobile and server/networking applications.

If you can’t make it to the live versions, still register and they will send you a link to the replay. I can also have SemiWiki bloggers attend them so they can share their opinions, observations, and experiences.

Posted on

Analog Bits and TSMC!

Analog Bits and TSMC!
by Daniel Nenni on 01-10-2017 at 12:00 pm
Categories: Analog Bits, FinFET, IP, TSMC

TSMC Wafer

As a long time semiconductor IP professional I can tell you for a fact that it is one of the most challenging segments of semiconductor design. Given the growing criticality of semiconductor IP, the challenges of being a leading edge IP provider are increasing and may be at a breaking point. The question now is: What does it take to be a successful leading edge semiconductor IP company?

First and foremost, you must have a high tolerance for pain! Not only do you compete with other IP companies, big and small, you compete with internally developed IP which is like selling shoes to a shoemaker.

Second, you have to have a VERY close “silicon proven” relationship with the foundries. All was well in the Semiconductor IP business until FinFETs came about. Not only are FinFETs a significant design challenge requiring early access to leading edge processes, the foundries have locked down that early access. Do you remember back at 28nm and above when the foundry processes were all “T like”? IP companies developed products at TSMC and ported them to UMC, SMIC, and Chartered making it much easier to scale your IP development, right? That portability is now gone with FinFETs and as we move down the process path to 7nm and 5nm the design challenges and security restrictions are growing rapidly, absolutely.

Third, your business model had better be mean and lean with the ability to pivot at a moment’s notice. The good news is that silicon proven commercial IP is much more attractive now that design cycles are tight, the tightest I have ever seen actually. I am also seeing more systems companies making their own chips using commercial IP. Then there is the semiconductor company consolidation which is a double edged sword. It is good news if your customer takes over your competitor’s customer and not so good news if it is the other way around. So you had better be nimble, you had better be quick, and that brings us to the poster child for a successful leading edge IP company: Analog Bits.

Founded in 1995 here in Silicon Valley, Analog Bits has zero external funding and has enabled billions of chips from .25 micron down to FinFETs via more than 350 customers worldwide and more than 70 unique processes. They are experts (1st time right) at low power mixed signal IP and a pioneer in Multi-Protocal SERDES. Analog Bits is also an ardent TSMC supporter (which is where I know them from) and a member of the exclusive “TSMC Partner of the Year” club.

In fact, Analog Bits presented twice at the previous TSMC OIP Ecosystem Forum. The first presentation was Silicon-proven, low power IP for TSMC 16nm FFC for Automotive to Datacenter SOC’s and the second was Design and Verification of 16nm FFC Low Power SERDES for Datacenter and Automotive Applications. The theme of course is leading edge SoC design for two of the hottest semiconductor vertical markets. If you click on the links it will take you to the abstracts on the TSMC site. To see the full presentation you will need to have a TSMC account or you can contact Analog Bits and talk to them directly.

You can hear a bit more about Analog Bits in the recruitment video below. They are hiring big time:

Posted on

The 2017 Leading Edge Semiconductor Landscape

The 2017 Leading Edge Semiconductor Landscape
by Scotten Jones on 12-27-2016 at 6:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC

In early September of 2016 I published an article “The 2016 Leading Edge Semiconductor Landscape” that proved to be very popular with many views, comments and reposting’s. Since I wrote that article a lot of new data has become available enabling some projections to be replaced by actual values and new analysis and projections to be made.
Continue reading “The 2017 Leading Edge Semiconductor Landscape”

Posted on

Advanced Semiconductor Process Cost Trends

Advanced Semiconductor Process Cost Trends
by Scotten Jones on 12-13-2016 at 4:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC

The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of the status and a future forecast.
Continue reading “Advanced Semiconductor Process Cost Trends”

Posted on

Design for Fanout Packaging

Design for Fanout Packaging
by Bernard Murphy on 12-12-2016 at 12:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In constant pursuit of improved performance, power and cost, chip and system designers always want to integrate more functions together because this minimizes inter-device loads (affecting performance and power) and bill of materials on the board (affecting cost). However it generally isn’t possible to integrate everything onto one piece of silicon; digital, RF, memory and sensor functions typically must be built using incompatible processes and often depend on isolation from other functions. So product teams have turned to advanced packaging options in which multiple die, potentially built in different processes, can be integrated within a package. This still reduces inter-die loads significantly and still results in a single device at the board level.

Among the best-known approaches, 2.5D and 3D packaging are particularly popular for memory, FPGA and CPU/GPU applications. But another related packaging methodology, Fanout Wafer-Level Packaging (burdened with the unappealing abbreviation FOWLP) is already seeing wider adoption in automotive, RF and mobile applications (as seen in recent iPhones).

Avoiding the gory details, the essence of FOWLP is to embed die side-by-side in an epoxy mold compound with IO pads exposed; routing distribution layers (RDLs) are then grown over the exposed faces to connect die together, and to connect to locations for external IOs. TSVs and traditional interposers are not required, which reduces cost and allows for thinner packages.

This might be no more than an interesting alternative for packaging were it not for the fact that TSMC (among other foundries) now offers an integrated FOWLP solution they call Integrated Fanout or InFO (a much more appealing abbreviation). You can fab die with TSMC and you can integrate them into an InFO package also with TSMC. This contrasts with FOWLP solutions offered by out-sourced assembly and test (OSAT) companies who obviously do not fab die themselves.

OSATs provide features that integrated foundry solutions do not (such as integrating die from multiple foundries) but with multiple suppliers in a package customers are ultimately responsible for managing yield issues. However, with an integrated solution like InFO and sufficient market muscle to force partner die providers to fab at TSMC, managing yield should be more tractable. As a friend once told me, it’s good to have just one throat to choke when you run into problems.

Which brings me to the EDA tooling you need to design this kind of integration. FOWLP packaging methods blur the line between die design (using Linux-based design tools with all kinds of disciplined design and verification automation) and package design (usually PC-based and driven more by expert judgment than automation). More information must be communicated between package designers and chip designers and it is increasingly common to expect some level of co-design between these two, to optimize die pinouts and power distribution networks for example. Analysis at the package level must also be much more comprehensive, considering electromigration, thermal, stress and warping effects, requiring more comprehensive analysis than commonly expected in package design.


Mentor offers a very complete flow covering both design and signoff verification of FOWLP systems, starting with the Xpedition Package integrator. In conventional PCB applications Xpedition helps IC, packaging, and printed circuit board (PCB) co-design teams visualize and optimize complex single or multi-chip packages integrating silicon on board platforms. In FOWLP flows, the platform offers a single layout tool supporting fan-out as well as PCB, MCM, silicon photonics, RF and BGA designs. Users can drive rule-based I/O-level optimization and perform pin and ball-out studies from their respective domains, visualizing the impact across the complete system.

Electrical modeling and analysis of the package (die, package, substrate, board, etc.) is provided by Mentor’s HyperLynx simulation software. This analyzes design rule checks, power and signal integrity, EM, EMI and thermal; it also provides package model creation for use at the PCB level.

All of that is very necessary to design the integration but how do you get to a concept of signoff in these flows? Yields can’t be guaranteed or improved unless there is some kind of contract between customer and packager. In the IC world, this is accomplished through process design kits (PDKs). The customer signs off a design based on a PDK and the foundry guarantees their performance based on that signoff.

Mentor has introduced an approach for sign-off quality physical verification of packages which they call an assembly design kit (ADK). The purpose is similar to a PDK—to enable a contract for manufacturability and performance. What makes that happen, in both PDKs and ADKs, are standardized rules that ensure consistency across a process, qualified tool flows, interface formats, input/output formats—in short, everything a designer needs for successful design, tested and qualified and proven to produce working products. In one sense the ADK concept is not new. OSATs are already providing rules and tools for their own solutions. But the Mentor approach offers the hope of standardized requirements definitions, usable by OSAT and foundry providers and by EDA tool providers, just like we now expect for PDKs.


The platform to implement those signoff checks is the Calibre 3DSTACK functionality in Calibre nmPlatform. This is not just the IC Calibre you know and love, since it has to deal with a much more complex verification space. It requires a better understanding of the z-dimension than required for IC design. It has to deal with non-Manhattan shapes common in package design. And it must understand a wider range of formats such as ODB++ and comma-separated values for package netlists. Given these capabilities, package DRCs, package LVS, and interface checks can all be combined into a single Calibre 3DSTACK deck and checked in one run. The only individual runs required are for die-specific DRCs and LVS.

Calibre 3DSTACK is designed to support FOWLP designs for OSATs and foundries through ability to express die-by-die and package layer characteristics and rules. This is a big topic for which there’s a lot more detail than I have room (or expertise) to cover here. I recommend you read the more detailed white paper from Mentor to get a better understanding of capabilities and requirements.

More articles by Bernard…