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ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?

ASML – In Line Qtr but big bookings – Logic Strong! Memory ? EUV?
by Robert Maire on 10-20-2019 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services, TSMC

ASML in line QTR with big Orders
Near term slippage w long term upside
Logic is strong but memory recovery unknown
EUV is finally a reality/commercialized

In line quarter- supplier slippage expected in Q4
Results were revenues of Euro 3B and EPS of Euro 1.49, more or less in line with earnings estimate if a tad bit light in revenue. Outlook for Q4 is Euro 4B with 4 EUV systems slipping into 2020 due to supplier issues (now resolved)

Logic is leading the recovery… Obviously TSMC
Over 70% of orders are from foundry/logic customers as everyone is getting in the queue now that EUV is in commercial production. TSMC is the leader in real EUV and likely accounts for the largest portion of those future EUV orders

Memory still an unknown
Several months ago we said that the recovery would be led by logic as the memory recovery would take longer than most people expected due to the sidelined capacity amid excess supply and weak pricing.

This is becoming clearer to most people as we have heard from Micron, which was weaker than many expected and now clearly hearing from ASML that memory business remains weak with unknown timing of a recovery.
Some are expecting a recovery early in 2020, but we would not get our hopes up as it could take all of 2020 to get memory back on track.

Huge orders Euro 5B and 23 EUV tools
ASML is selling out its capacity very quickly as we are now seeing a virtual avalanche of orders. EUV has been proven and no customer wants to be excluded from the party or perhaps run out of capacity.

Part of the huge ramp is the large ramp in the numbers of layers in a chip made with EUV, going from a few ,like 3-5, going to 12 to 15 (depending upon whom you believe). Basically the number of tools has to increase proportionately with the number of layers. Memory is still a long way away from using EUV so in our view the current memory weakness, while impacting DUV and immersion is not slowing down EUV.

In a perverse way, the weakness in EUV demand for memory is likely of benefit to the logic side of the industry as it doesn’t compete for limited EUV tool availability.

40 plus EUV tools should be very easy to book for next year as we are more than halfway there. I think we can get there even without any memory recovery.

Not worried about supplier slippage
Given the complexity of an EUV tool and the huge supply chain we are certainly going to see issues here and there. The fact that its only a one quarter slip suggests its not a big or systemic problem.

We would likely take a longer term view as to the overall trend and worry less about the actual ship date and whether it falls within one quarter or another. ASML is not in a “turns” business like dep and etch or other relatively simple to assemble tools.

It down to production execution
As we are now past the milestone of actual commercial EUV production we are past the point of invention, luck, and pain and suffering trying to get the technology to work and more focused on production issues and the ramp of manufacturing.

To be sure, there are still many issues out there, pellicles, resist, reticle inspection, but what we have is working well enough to push forward on the number of layers using EUV and thus more tools.

We have covered ASML for almost 25 years with much of that history watching the EUV saga play out, so it is interesting to see the final conclusion (or perhaps beginning) of an era.

The stock –
Priced for perfection in an imperfect world, but still pretty good. ASML’s stock has steadily climbing based on the view of a recovering chip sector. Some stocks in the space have gotten a bit ahead of themselves but we think ASML’s value increase is justified given where we are with EUV, the strong logic/foundry demand and overall positioning in the market. Some investors may be unhappy with the slippage, but we are less concerned as you have to look at the longer term.

Some investors may be unhappy with a quarter that was just “in line” but given the memory weakness, we think “in line” is very good performance as ASML is working with one hand (memory) tied behind its back.

Overall we remain constructive on the stock and would look at pull backs or weakness as an opportunity to build or enhance a position going forward.
The stock is not cheap but the performance and positioning support the valuation.

We think that ASML has the lowest China/US trade problem exposure (though not zero) and EUV sales are less impacted by near term economic gyrations as the backlog is likely very strong. All in all a relatively defensive position in a very cyclical industry.

Summary
ASML remains a virtual monopoly, with a huge defensive moat, upside potential in revenues and margins and a leading technology position. We expect margins and therefore profitability to increase steadily as EUV ramps over the next few years leading to long term upside. It remains one of our top picks in large caps in the space.

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TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution

TSMC – Solid Q3 Beat Guide- 5G Driver – Big Capex Bump – Flawless Execution
by Robert Maire on 10-19-2019 at 6:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

TSMC puts up solid QTR, Capex increase for 5NM and capacity increase, 5G/mobile remains driver- HPC good 7NM, 27% of revs- Very nice margins!

In line quarter-Good guide
TSMC reported revenues of $9.4B and EPS of $0.62 , more or less in line with expectations, perhaps a touch below ” whisper” expectations which had been growing along with the lead times for 7NM. Gross margin was a nice 47.6%.
Q4 is expected to be between $10.2B and $10.3B with gross margins between 48% and 50%. This revenue outlook is well above current street expectations.

Large bump up in Capex
We have been talking about a logic led recovery, in chip equipment, given the strength at TSMC. TSMC bumped up their 2019 capex from $12.5B to $14 to $15B with initial outlook for 2020 to be similar to 2019.

This suggests a bit of a hockey stick like capex spend in the current Q4 of 2019.This hockey stick will show up in a better than expected guide from tool companies

We think this is likely a strong mix of not only 5NM spend but also 7NM capacity related spend given better than expected demand and long lead times currently seen by customers.

Capex intensity, currently at 40% is expected to come down in 2020 and further come down in 2021 to 30% to 35%

5G and mobile remains the big upside in demand
In our view, customers in the mobile space are all rushing to get to market first with 5G devices to try to stake a claim to market share and early dominance. This has created a strong “land rush” of orders to insure enough 5G chips to power those devices.

7NM was 27% of total sales which supports this strong demand and suggests strong pricing ability as well.

This is quite a strong ramp from the start of 7NM earlier in the year. We are sure that HPC (read that as AMD) is also clearly helping to drive demand over the top.

Smartphone was 49% of revenue with HPC at 29%.

We don’t think any significant portion of sales was due to inventory build or channel stuffing as fears of trade ware related cut offs have subsided in the market.

TSMC winning on both yield and packaging
In our view, we think that TSMC is attracting more customers and thus the longer lead times as they have both better yields and better packaging technology.

We think Samsung has had more struggles with yield and coming up to speed despite (and potentially because of ) EUV implementation.

We also think that TSMC’s advanced capabilities in packaging allow it to offer customers more and better options in 2.5 and 3D packaging.

As customers look for other strategies outside of Moore’s law scaling, such as “chiplets”, these packaging options become a critical differentiating and enabling technology. Some customers, such as AMD, are currently banking on advantages of a “chiplet” architecture.

Collateral impact on equipment companies
TSMC’s report , and large capex increase, confirms our view that there is a strong near term pick up in equipment demand despite memory “sucking wind”.

We think most equipment suppliers will report at least in line or likely better than expected results in the current quarter but more importantly will guide even higher going forward as orders from TSMC hit their order books.

This is very much in line with our “logic/foundry led recovery” that we have talked about for several months. While not a rip roaring semicap recovery, its better than the bouncing along the bottom that the industry has been stuck with and importantly puts an upward bias on business even though the slope may be low without memory.

The Stock – Nice quarter, but perhaps not up to the unrealistic expectations of the market
Its clear that chip stocks have been on a tear and along with the stocks, and so have expectations. Much of this in TSMC’s case is a combination of Apple talking about increasing supplier orders by 10% along with the extended lead times at TSMC 7NM. We think expectations and the stock both got a little bit ahead of themselves such that when the company reported an excellent quarter, such as it did, that investors were unimpressed as it didn’t blow away numbers.

We would use any weakness as an entry point to add to positions in TSMC.

They are now more dominant in foundry than ever before and if anything they are lengthening their lead over number two Samsung. Near term demand looks very good, margins are good and getting better.

Most importantly, TSMC continues to push Moore’s Law forward without any visible hiccups or delays…..perhaps they make it look too easy…..perhaps they should have a one quarter “oops” to make them look human and reset investors expectation of perfect performance in technology execution.

They have a very long runway of upside in 5G , with little competition, ahead of them. They are also the “real” engine behind AMD’s success and will get their fair share of the upside associated with that and other HPC business.

We like companies that have dominant or monopolistic-like positions, great execution on technology with a strong defensive “moat” . All this usually combines to show up in financial performance and future upside which we clearly have with TSMC.

We continue to be a buyer of the stock and would be more aggressive on pullbacks. Our only significant cautions would be trade and macro economic risk that all chip companies share.

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My Top Three Reasons to Attend IEDM 2019

My Top Three Reasons to Attend IEDM 2019
by Scotten Jones on 10-11-2019 at 6:10 am
Categories: Events, FD-SOI, FinFET, Foundries, Intel Foundry, TSMC

The International Electron Devices Meeting is a premier event to learn about the latest in semiconductor process technology. Held every year in early December is San Francisco this years conference will be held  from Decembers 7th through December 11th. You can learn more about the conference at their web site here.

This is a must attend conference for me every year.

The following are a few of the announced papers I am particularly excited about:

(1) TSMC to Unveil a Leading-Edge 5nm CMOS Technology Platform: TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channelmobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in highspeed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20. (Paper #36.7, “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and HighMobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al., TSMC)

(2) Intel Says Heterogeneous 3D Integration Can Drive Scaling: CMOS technology requires both NMOS and PMOS devices, but the performance of PMOS lags NMOS, a mismatch which must be addressed in order to wring every last bit of performance and energy efficiency from future chips. One way to do that is to build PMOS devices with higher-mobility channels than their NMOS counterparts, but because these are built from materials other than silicon (Si) which require different processing, it is challenging to build one type without damaging the other. Intel researchers got around this with a 3D sequential stacking architecture. They first built Si FinFETNMOS transistors on a silicon wafer. On a separate Si wafer they fabricated a single-crystalline Ge film for use as a buffer layer. They flipped the second wafer, bonded it to the first, annealed them both to produce a void-free interface, cleaved the second wafer away except for the Ge layer, and then built gate-all-around (GAA) Ge-channel PMOS devices on top of it. There was no performance degradation in the underlying NMOS devices, and in an inverter test circuit the PMOS devices demonstrated the best Ion-Ioff performance ever reported for Ge-channel PMOS transistors (Ion=497 µA/µm and Ioff=8nA/µm at 0.5V). The researchers say these results show that heterogeneous 3D integration is promising for CMOS logic in highly scaled technology nodes. (Paper #29.7, “300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low-Power, High-Performance Logic Applications,” W. Rachmady et al., Intel.)

(3) Versatile 22nm STT-MRAM Technology: Many electronics applications require fast nonvolatile memory (NVM), but embedded flash, the current dominant technology, is becoming too complex and expensive to scale much beyond 28nm. A type of embedded NVM known as STT-MRAM has received a great deal of attention. STT-MRAM uses magnetic tunnel junctions (MTJs) to store data in magnetic fields rather than as electric charge, but this ability decreases as temperature increases. That makes STT-MRAM both challenging to build – it is fabricated in a chip’s interconnect and must survive high-temperature solder reflow – and also to use in applications such as automotive, where thermal specifications are demanding and the ability to resist outside magnetic fields is critical. TSMC will describe a versatile 22nm STT-MRAM technology that operates over a temperature range of -40ºC to 150ºC and retains data through six solder reflow cycles. It demonstrated a 10-year magnetic field immunity of >1100 Oe at 25ºC at a 1ppm error rate, and <1ppm when in a shield-in-package configuration. The researchers say that by trading off some of the reflow capability and using smaller MTJs, even higher performance can be achieved (e.g., 6ns read times/30ns write times), making them appealing for artificial intelligence inference engines. (Paper #2.7, “22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability and Magnetic Immunity and with Performance and Shielding Options,” W. Gallagher et al., TSMC)

About IEDM
With a history stretching back more than 60 years, the IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.

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A Future Vision for 3D Heterogeneous Packaging

A Future Vision for 3D Heterogeneous Packaging
by Daniel Nenni on 10-07-2019 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

At the recent Open Innovation Platform® Ecosystem Forum in Santa Clara, TSMC provided an enlightening look into the future of heterogeneous packaging technology.  Although the term chiplet packaging is often used to describe the integration of multiple silicon die of potentially widely-varying functionality, this article will use the term heterogeneous packaging.  The examples below illustrate integration of both large and small die, DRAM die, and a full high-bandwidth memory die stacks (HBM2), much richer in scope than would commonly be designated as a chiplet.  Dr. Douglas Yu, Vice President of Integrated Interconnect and Packaging at TSMC, provided a review of current TSMC heterogeneous packaging offerings, and a 3D package vision that could be best described as “More-than-More-than-Moore”.

Doug began with the well-understood realization that the pace at which the cost-per-transistor has improved with IC process technology scaling has slowed.

Figure 1.  The rate of cost-per-transistor improvements with process technology scaling has slowed.  (Source:  TSMC)

There are certainly ongoing product PPA benefits to scaling, but the ultimate cost for the total system functionality may drive system designers to pursue heterogeneous packaging alternatives.

CoWoS

The first heterogeneous packaging offering from TSMC was Chip-on-Wafer-on-Substrate ( CoWoS® ).  A cross-section of a CoWoS® package is illustrated below.

Figure 2.  CoWoS® package integration  (Source:  TSMC)

A silicon interposer provides the interconnects between the die, with through-silicon vias (TSV) to the substrate below.  Doug highlighted the recent advances in CoWoS® technology in production, specifically the ability to fabricate the interposer at 2X the max reticle size for wafer lithography.

Figure 3.  CoWo®S support for a silicon interposer greater than the single max-reticle size   (Source: TSMC)

InFO-PoP

Doug reviewed TSMC’s cost effective heterogeneous integration package, based on the Integrated FanOut (InFO) technology.  The original InFO offering provided (reconstituted) wafer-level redistribution layer connectivity to extended bump locations outside the die perimeter.  The newer InFO-PoP package cross section is illustrated below.

Figure 4.  InFO-PoP cross section  (Source:  TSMC)

The extension of the InFO molded package beyond the embedded die is used for Through-InFO vias (TIV) between the top die and the redistribution layer connections.

SoIC®

A more recent TSMC heterogeneous package innovation involves the transition from microbump connections between die and substrate to a bumpless (thermo-compression) bond between direct die connections – see the figure below for a comparison between microbump and bumpless attach. TSMC-SoIC® is an innovative frontend wafer-process-based platform that integrates multi-chip, multi-tier, multi-function and mix-and-match technologies to enable high speed, high bandwidth, low power, high pitch density, and minimal footprint and stack-height heterogeneous 3D IC integration.

Figure 5.  Comparison of bump and bumpless technology characteristics, and SoIC® package cross-section  (Source:  TSMC)

Through silicon vias provide connection to bumps, part of the final back-end package assembly flow.  The density and electrical characteristics of the bumpless attach technology are far superior.  (Here’s a previous semiwiki article that describes the TSMC SoIC® package technology – link.)

https://semiwiki.com/semiconductor-manufacturers/tsmc/8150-tsmc-technology-symposium-review-part-ii/

Future Vision

Doug provided a vision for heterogeneous packaging, which combines the unique advantages of the technologies described above.  The figure directly below depicts a bumpless SoIC® composite as part of a larger InFO or CoWoS® package, integrating additional die and/or HBM memory stacks.

The second figure below illustrates multiple levels of (thinned) die using bumpless attach for subsequent back-end package assembly.  Doug referred to this multi-level SoIC® solution as part of the transition from 3D system integration to full 3D system scaling.

Figure 6.  SoIC® integration in a subsequent InFO or CoWoS® package  (Source:  TSMC)

Figure 7.  Multi-level bumpless die integration à 3D system scaling  (Source:  TSMC)

The heterogeneous packaging technology vision presented by TSMC will truly provide system architects with great opportunities for continued scaling.  In addition to traditional monolithic die PPA considerations for technology selection, this vision offers additional opportunities for system-level functional integration and packaging cost optimizations.  It will be fascinating to see how these heterogeneous packaging offerings impact future system designs.

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A Review of TSMC’s OIP Ecosystem

A Review of TSMC’s OIP Ecosystem
by Daniel Nenni on 10-06-2019 at 10:00 am
Categories: Events, Foundries, TSMC
1 Comment

Each year, TSMC conducts two events – the Technology symposium in the Spring and the Open Innovation Platform (OIP) ® Ecosystem Forum in the Fall.  Yet, what is the OIP ecosystem?  What does it encompass?  And, how does the program differentiate TSMC from other foundries?  At the recent OIP Forum in Santa Clara, Suk Lee, Senior Director, TSMC Design Infrastructure Management Division, presented a review of OIP, highlighting the breadth of technology and support available for TSMC process nodes.  Additionally, and very significantly, he described the extensive engineering investment made to develop and qualify new process design kit materials (PDK) and IP offerings.  Here are some of the highlights of Suk’s presentation.

Figure 1.  OIP partner overview  (Source:  TSMC)

OIP entails the collaboration between TSMC and numerous partners, spanning a range of technical facets of silicon foundry support:

  • EDA tool providers
  • IP developers
  • Design Center Alliance (DCA) providers, offering services ranging from system-level front-end design to back-end physical/test implementation
  • Value Chain Aggregators (VCA), additional service providers commonly offering a different set of capabilities, including assembly/test and supply chain management support

and, the newest aspect of OIP partnership, which was announced last year with the introduction of its OIP Virtual Design Environment (OIP VDE), lowering entry barriers of Cloud adoption for the customers of all sizes

  • Cloud service providers

To perhaps better distinguish between the DCA and VCA partners, Suk overlaid the previous chart on top of the Design Enablement and Process Development groups at TSMC – see the figure below.

 Figure 2.  OIP partner interactions with TSMC R&D  (Source:  TSMC)

Yet, these OIP designations are much more than companies enrolling with TSMC.  Suk emphasized the qualification requirements and ongoing monitoring to which each OIP partner is subjected, as illustrated below.

Figure 3.  Examples of OIP partner qualification requirements  (Source:  TSMC)

From TSMC’s own derivative of ISO9000 qualify management and assurance (aka, TSMC9000) to qualification of process interconnect technology definitions to ongoing certification of OIP service providers, there is a major emphasis on ensuring foundry customer success.

Perhaps the best illustration of OIP collaboration is the activity pursued with EDA partners during new process development.  This activity ensures new tool features and full methodology reference flow capabilities are qualified concurrently with initial process availability for IP developers and early end customer adopters.  Suk provided examples where new EDA tool attributes were defined, developed, and integrated into reference flows, driven by both process innovations (e.g., EUV lithography) and design reliability and manufacturability (e.g., via pillars, statistical analysis).  The figures below illustrate how the digital and custom design flows from EDA OIP partners were enhanced in support of these advanced process requirements.

Figure 4.  New EDA tool features addressing process requirements – digital flows  (Source:  TSMC)

Figure 5.  New EDA tool features addressing process requirements – custom implementation flows  (Source:  TSMC)

Engineers are skeptical by nature, seeking a silicon-proven demonstration of models, EDA tool features, and reference flows.  Suk highlighted the specific collaboration with ARM – for nearly a decade, TSMC and ARM have used leading ARM core IP as a testchip vehicle.  Full EDA (and IP) qualification reports are available at TSMC’s customer portal. On the day of OIP Forum, the two companies also announced the latest result of their collaboration, an industry-first 7nm silicon-proven chiplet system based on multiple Arm® cores and leveraging TSMC’s Chip-on-Wafer-on-Substrate (CoWoS®) advanced packaging solution.

 

Figure 6.  Screenshot of example EDA qualification reports on the TSMC portal   (Source:  TSMC)

With all the news relative to new process node announcements, it is easy to overlook the underlying activities and resources required to synchronize process availability with the companies supporting the related EDA, IP, and service provider ecosystem.  Suk’s presentation reminded the OIP Ecosystem Forum audience of the tremendous investment made as part of the effort to sustain Moore’s Law (for at least another node or two).  The focus that TSMC has applied to design enablement has truly been a differentiating characteristic of their corporate philosophy.

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TSMC OIP Overview and Agenda!

TSMC OIP Overview and Agenda!
by Daniel Nenni on 09-05-2019 at 6:00 am
Categories: Events, Foundries, TSMC

The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share practical, tested solutions to today’s design challenges. Success stories that illustrate TSMC’s design ecosystem best practices highlight the event.

More than 90% of last year’s attendees said that, “the forum helped me better understand TSMC’s Open Innovation Platform” and that “I found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies and joint design solutions to address your design challenges in High-Performance Computing (HPC), Mobile, Automotive and Internet-of-Thing (IoT) applications.

This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC and leading IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 70 member companies showcasing their products and services.

Date: Thursday, September 26, 2019 8:00 AM – 6:30 PM

Venue: Santa Clara Convention Center

Learn About:

  • Emerging advanced node design challenges including 5nm, 6nm, 7nm, 12FFC/16FFC, 16FF+, 22ULP/ULL, 28nm, and ultra-low power process technologies.
  • Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
  • Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
  • Ecosystem-specific TSMC reference flow implementations
  • New innovations for next generation product designs targeting HPC, mobile, automotive and IoT applications

Hear directly from ecosystem companies about their TSMC-specific design solutions. Network with your peers and more than 1,000 industry experts and end users.

The TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event.  Please register to attend. We look forward to seeing you at the event.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.

Agenda:

Join the TSMC 2019 Open Innovation Platform® Ecosystem Forum and hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!

08:00 – 09:00 Registration & Ecosystem Pavilion

09:00 – 09:20 Welcome Remarks

09:20 – 10:10 TSMC and its Ecosystem for Innovation

10:10 – 10:30 Coffee Break

REGISTRATION

Please click the paper title to see its abstract:
HPC & 3DIC Mobile & Automotive IoT & RF
10:30 – 11:00
TSMC 3DIC Design Enablement Updates
TSMC
TSMC EDA & IP Design Enablement Updates
TSMC
TSMC RF Design Enablement Updates
TSMC
11:00 – 11:30

Calibre in the Cloud – A Case study with AMD, Mentor & TSMC
Microsoft/AMD/Mentor

Functional Safety Analysis and Verification to meet the requirements of the Automotive market
Texas Instruments/Cadence

Simplify Energy Efficient designs with cost-effective SoC Platform
Dolphin Design
11:30 – 12:00

Optimizing FPGA-HBM in InFO_MS Structure
Xilinx/Cadence

Thermal-induced reliability challenge and solution for advanced IC design
ANSYS

Flexible clocking solutions in advanced FinFET processes from 16nm to 5nm
Silicon Creations
12:00 – 13:00 Lunch & Ecosystem Pavilion
13:00 – 13:30

Chiplets solutions using CoWoS and InFO with 112Gbps SerDes and HBM2E/3.2Gbps for AI, HPC and Networking
GUC

Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production
AMD/Mentor

Developing AI-based Solutions for Chip Design
Synopsys
13:30 – 14:00

Realizing Adaptable Compute Platform for AI/ML and 5G with Synopsys’ Fusion Design Platform
Xilinx/Synopsys

Comprehensive ESD/Latch-up reliability verification for IP & SoC Designs
NXP/Silicon Frontline/Mentor

Reliable, Secure and Flexible OTP solutions in TSMC for IoT, AI and Automotive Applications
eMemory
14:00 – 14:30

HBM2E 4gbps I/O Design Techniques in 7nm & Below Nodes
Open-Silicon

Sensor fusion and ADAS SOC designs in TSMC 16FFC and N7
Cadence

High-Speed Interface IP PAM-4 56G/112G Ethernet PHY IP for 400G and Beyond Hyperscale Data Centers
Synopsys
14:30 – 15:00

Pushing 3GHz Performance of TSMC N7 Arm Neoverse N1 CPU using the Cadence Digital Flow
Cadence/Arm

AWS Cloud enablement of design characterization flows using Synopsys® Primetime® & HSPICE®
Xilinx/Synopsys

Automotive IP Functional Safety – A Verification Challenge
Cadence
15:00 – 15:30 Coffee Break & Ecosystem Pavilion
15:30 – 16:00

Large Scale Silicon Photonic Interconnects for Mass Market Adoption
HPE/Mentor

A New Era of MIPI D-PHY and C- PHY: Automotive Applications
M31

Best practices for Arm Cortex CPU energy efficient implementation flows
Arm
16:00 – 16:30

Photonics Coming of Age: From Laboratory to Mainstream Applications
Cadence/Lumerical

Integrating ADAS Controllers with Automotive-Grade IP for TSMC N7
Synopsys

The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm
Moortec
16:30 – 17:00

Accelerating Semiconductor Design Flows with EDA on the Cloud
Astera Labs/AWS

Arm automotive physical IP addresses new feature and functionality demands
Arm

Developing AI Accelerators for TSMC N7
Synopsys
17:00 – 17:30

Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in TSMC 7nm FinFET Process Technology
Synopsys/Arm

Cloud-based Characterization with Cadence Liberate Trio Characterization Suite and Arm-based Graviton
Cadence
Optimize SOC designs while enabling faster tapeouts by closing chip integration DRC issues early in the design cycle
MaxLinear/Mentor
17:30– 18:30 Social Hour

 

TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.

TSMC serves its customers with annual capacity of about 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities, and is headquartered in Hsinchu, Taiwan.

REGISTRATION

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TSMC in the Cloud Update #56thDAC 2019

TSMC in the Cloud Update #56thDAC 2019
by Daniel Nenni on 06-13-2019 at 10:00 am
Categories: Events, Siemens EDA, TSMC
2 Comments

During my Taiwan visit, prior to Las Vegas, I was fortunate to spend time with Willy Chen and Vivian Jiang to prepare for the cloud panel I moderated at #56thDAC. Willy and Vivian are part of the ever-important Design Infrastructure Marketing Division of TSMC, which includes the internal and external cloud efforts. TSMC first announced their external cloud offering last year: TSMC announces initial availability of Design-in-the-Cloud via OIP VDE and OIP Ecosystem Partners and has made follow-up announcements with all of the key vendors and participated in multiple cloud panels last week in Las Vegas. Make no mistake, TSMC is a semiconductor cloud pioneer, absolutely.

There are however a couple of things I would like to point out as an objective semiconductor cloud insider. I first heard of TSMC seriously considering the cloud more than 10 years ago. Back then the big hurdle was customer security and having been through TSMC’s security protocol for EDA and IP vendors many times I can tell you TSMC is all about security. But TSMC is also all about enabling customers of all types and getting high quality wafers to the masses and today that means cloud.

Another interesting point in the semiconductor cloud transformation is that systems companies are driving the leading edge foundry business instead of traditional fabless chip companies. Some of these systems companies are actually cloud based companies (Google, Microsoft, Amazon, and Facebook) so there is no security concern there. In fact, cloud security is above and beyond anything we have ever seen in the semiconductor industry and TSMC knows this by direct experience with their cloud customers.

As more systems companies use the cloud for chip design the fabless companies have no choice but to follow. The cloud company chip designers are the extreme case. They can do simulations and verification in hours versus days or weeks. Imagine being able to run a SPICE simulation or characterization run in an hour versus over night?

As I mentioned before, investment in fabless chip companies more than tripled in 2017 and doubled again in 2018. Similar to the fabless transformation, where semiconductor companies no longer had to build fabs, today’s fabless companies don’t have to buy computers and tools, they just go to the cloud where TSMC and EDA is already there waiting for them, absolutely.

One of the more interesting cloud events at #56thDAC was the Mentor Calibre Luncheon (FREE FOOD). SemiWiki Blogger Tom Simon sat in front of me and will blog this in more detail so spoiler alert: Willy Chen was on the panel and he talked about TSMC cutting down the DRC runtime of an N5 testchip from 24 hours to 4 hours using Azure Cloud.  AMD was on the panel and they talked about doing the same thing with their N7 products scaling to 4000 CPU cores using a Microsoft Azure VM (which is an AMD EPYC based server).

Admittedly the AMD presentation was a little self-serving but my takeaway was that AMD partnering with TSMC and pivoting to the cloud for chip design before their much bigger competitors do is a VERY big deal.

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#56DAC – What’s New with Custom Design Platform

#56DAC – What’s New with Custom Design Platform
by Daniel Payne on 06-12-2019 at 10:00 am
Categories: Events, Synopsys, TSMC

Dave Reed, Synopsys

TSMC attends DAC every year and they do something very savvy, it’s a theatre where they invite all of their EDA and IP partners to present something of interest, followed by a drawing for a prize. At the end of the day they even have a nice prize, like a MacBook Air, which I didn’t win. On Wednesday I watched Dave Reed of Synopsys present an update on the Custom Design Platform.

Dave Reed, Synopsys

Tools in the Custom Design Platform include:

Back in April they announced that these tools were certified by TSMC for the 5nm FinFET process node, which is always a big deal for IC design teams pushing the bleeding edge because you need your EDA tools ready.

The integration between these tools is tight, so the phrase used is DRC Fusion or Extraction Fusion, because users don’t want to wait hours streaming data out of one tool and made compatible with the next tool in the flow. Adoption of the Custom Compiler tool increased this past year, now with 100 logos and 3,000 users, and all internal Synopsys IP designs use their own tools.

Analog IC designers know that layout parasitics will affect the performance, accuracy and reliability of their circuits, so the Synopsys flow allows for early use of parasitic estimates, followed by partial extraction and fully extracted netlists.

Each new, smaller process node has an increase in circuit simulations and increase in parasitics, so FineSim can be used to simulate circuits like SERDES, PLL and ADC, now about 3X faster than before. Plus, they’ve added RF simulation to FineSim, so you have another choice than HSPICE.

Automating the layout of analog design is a noble quest, tried by many vendors in the past, so Synopsys continues with a template-based approach where expert layout designers capture their best practices, allowing for transistor size changes. All this is done without having to write code, or becoming a computer science major. I asked Dave about the CiraNova technology that they acquired years ago, and it’s still be used under the hood for layout automation.

IC designers used to work in either a digital or an analog environment, with tedious file interchanges between them, but not any more because Synopsys allows seamless use between the digital flow of IC Compiler II and the analog flow of Custom Compiler. DRC checking can be done either in batch mode or even interactively, saving you time.

Summary

If the Custom Design Platform can be used internally at Synopsys for creating all of their own IP in TSMC nodes at 28nm all the way down to 5nm, then it’s going to work for your project too. This is a competitive market segment and Synopsys keeps plugging away, year by year, making it easier to reach design closure through clever automation.

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In Their Own Words: TSMC and Open Innovation Platform

In Their Own Words: TSMC and Open Innovation Platform
by Daniel Nenni on 06-01-2019 at 8:00 am
Categories: Foundries, TSMC

TSMC, the largest and most influential pure-play foundry, has many fascinating stories to tell. In this section, TSMC covers some of their basic history, and explains how creating an ecosystem of partners has been key to their success, and to the growth of the semiconductor industry.

The history of TSMC and its Open Innovation Platform (OIP)® is, like almost everything in semiconductors, driven by the economics of semiconductor manufacturing. Of course, ICs started 50 years ago at Fairchild (very close to where Google is headquartered today, these things go in circles). The planarization approach, whereby a wafer (just 1” originally) went through each process step as a whole, led to mass production. Other companies such as Intel, National, Texas Instruments and AMD soon followed and started the era of the Integrated Device Manufacturer (although we didn’t call them that back then, we just called them semiconductor companies).

The next step was the invention of ASICs with LSI Logic and VLSI Technology as the pioneers. This was the first step of separating design from manufacturing. Although the physical design was still done by the semiconductor company, the concept was executed by the system company. Perhaps the most important aspect of this change was not that part of the design was done at the system company, but rather the idea for the design and the responsibility for using it to build a successful business rested with the system company, whereas IDMs still had the “if we build it they will come” approach, with a catalog of standard parts.

In 1987, TSMC was founded and the separation between manufacture and design was complete. One missing piece of the puzzle was good physical design tools and Cadence was created in 1988 from the merger of SDA and ECAD (and soon after, Tangent). Cadence was the only supplier of design tools for physical place and route at the time. It was now possible for a system company to buy design tools, design their own chip and have TSMC manufacture it. The system company was completely responsible for the concept, the design, and selling the end-product (either the chip itself or a system containing it). TSMC was completely responsible for the manufacturing (usually including test, packaging and logistics too).

At the time, the interface between the foundry and the design group was fairly simple. The foundry would produce design rules and SPICE parameters for the designers; the design would be given back to the foundry as a GDSII file and a test program. Basic standard cells were required, and these were available on the open market from companies like Artisan, or some groups would design their own. Eventually TSMC would supply standard cells, either designed in-house or from Artisan or other library vendors (bearing an underlining royalty model transparent to end users). However, as manufacturing complexity grew, the gap between manufacturing and design grew too. This caused a big problem for TSMC: there was a lag from when TSMC wanted to get designs into high volume manufacturing and when the design groups were ready to tape out. Since a huge part of the cost of a fab is depreciation on the building and the equipment, which is largely fixed, this was a problem that needed to be addressed.

At 65 nm TSMC started the Open Innovation Platform (OIP) program. It began at a relatively small scale but from 65 nm to 40 nm to 28 nm the amount of manpower involved went up by a factor of 7. By 16 nm FinFET, half of the design effort is IP qualification and physical design because IP is used so extensively in modern SoCs, OIP actively collaborated with EDA and IP vendors early in the life-cycle of each

process to ensure that design flows and critical IP were ready early. In this way, designs would tape-out just in time as the fab was starting to ramp, so that the demand for wafers was well-matched with the supply.

In some ways the industry has gone a full circle, with the foundry and the design ecosystem together operating as a virtual IDM. The existence of TSMC’s OIP program further sped up disaggregation of the semiconductor supply chain. Partly, this was enabled by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the SoC era, the amount of IP on each chip was beyond the capability or the desire of each design group to create. But, especially in a new process, EDA and IP qualification was a problem.

On the EDA side, each new process came with some new discontinuous requirements that required more than just expanding the capacity and speed of the tools to keep up with increasing design size. Strained silicon, high-K metal gate, double patterning and FinFETs each require new support in the tools and designs to drive the development and test of the innovative technology.

On the IP side, design groups increasingly wanted to focus all their efforts on parts of their chip that differentiated them from their competition, and not on re-designing standard interfaces. But that meant that IP companies needed to create the standard interfaces and have them validated in silicon much earlier than before.

The result of OIP has been to create an ecosystem of EDA and IP companies, along with TSMC’s manufacturing, to speed up innovation everywhere. Because EDA and IP groups need to start work before everything about the process is ready and stable, the OIP ecosystem requires a high level of cooperation and trust.

When TSMC was founded in 1987, it really created two industries. The first, obviously, is the foundry industry that TSMC pioneered before others entered. The second was the fabless semiconductor companies that do not need to invest in fabs. This has been so successful that two of the top 10 semiconductor companies, Qualcomm and Broadcom, are fabless and all the top FPGA companies are fabless.

The foundry/fabless model largely replaced IDMs and ASIC. An ecosystem of co-operating specialist companies innovates fast. The old model of having process, design tools and IP all integrated under one roof has largely disappeared, along with the “not invented here” syndrome that slowed progress since ideas from outside the IDMs had a tough time penetrating. Even some of the earliest IDMs from the “Real men have fabs” era have gone “fab lite” and use foundries for some of their capacity, typically at the most advanced nodes.

Legendary TSMC Chairman Morris Chang’s “Grand Alliance” is a business model innovation of which OIP is an important part, gathering all the significant players together to support customers—not just EDA and IP, but also equipment and materials suppliers, especially for high-end lithography.

Digging down another level into OIP, there are several important components that allow TSMC to coordinate the design ecosystem for their customers.

  • EDA: the commercial design tool business flourished when designs got too large for hand-crafted approaches and most semiconductor companies realized they did not have the expertise or resources in-house to develop all their own tools. This was driven more strongly in the front-end with the invention of ASIC, especially gate-arrays; and then in the back end with the invention of
  • IP: this used to be a niche business with a mixed reputation, but now is very important with companies like ARM, Imagination, CEVA, Cadence, and Synopsys, all carrying portfolios of important IP such as microprocessors, DDRx, Ethernet, flash memory and so on. In fact, large SoCs now contain over 50% and sometimes as much as 80% TSMC has well over 5,500 qualified IP blocks for customers.
  • Services: design services and other value-chain services calibrated with TSMC process technology helps customers maximize efficiency and profit, getting designs into high volume production rapidly
  • Investment: TSMC and its customers invest over $12 billion a year. TSMC and its OIP partners alone invest over $1.5 billion. On advanced lithography, TSMC has further invested $1.3 billion in

Processes are continuing to get more advanced and complex, and the size of a fab that is economical also continues to increase. This means that collaboration needs to increase as the only way to both keep costs in check and ensure that all the pieces required for a successful design are ready just when they are needed.

TSMC has been building an increasingly rich ecosystem for over 25 years and feedback from partners is that they see benefits sooner and more consistently than when dealing with other foundries. Success comes from integrating usage, business models, technology and the OIP ecosystem so that everyone succeeds. There are a lot of moving parts that all have to be ready. It is not possible to design a modern SoC without design tools, more and more SoCs involve more and more 3rd party IP, and, at the heart of it all, the process and the manufacturing ramp with its associated yield learning all needs to be in place at TSMC.

The proof is in the numbers. Fabless growth in 2013 is forecasted to be 9%, over twice the increase in the overall industry at 4%. Fabless has doubled in size as a percentage of the semiconductor market from 8% to 16% during a period when the growth in the overall semiconductor market has been unimpressive. TSMC’s contribution to semiconductor revenue grew from 10% to 17% over the same period.

The OIP ecosystem has been a key pillar in enabling this sea change in the semiconductor industry.

TSMC 2019 Update

2019 TSMC Technology Symposium Review Part I

TSMC Technology Symposium Review Part II

 

Global Unichip Corporation

Another facet of TSMC is GUC, Global Unichip Corporation. It is a partially owned subsidiary and also an important partner, providing design services and allowing TSMC themselves to continue to be a pure-play foundry. GUC was founded in 1998 with 10 employees as what has come to be known as a “Design Service” company. It ramped fast and by 2000 it employed over 100 people.

The years between 2003 and 2010 were milestone years for GUC, representing a period of unprecedented growth. The era was marked by a strengthening of both business and technology relationships with the largest semiconductor foundry in the world, TSMC. That relationship set GUC on firm growth, bringing over the core of today’s management and the business strategy that guides the company today.

In 2003, TSMC assumed an ownership stake in GUC. But the foundry leader’s investment went far beyond financial investment. Part of its strategy to enhance the return on its investment was to move GUC to a global business strategy and put it on the road to being an advanced technology leader.

The technology model, and the business model that accompanied it, soon began to gain traction. Prior to 2003, much of GUC’s business came from the consumer electronics companies who tended to utilize more mature technologies and were primarily located in Taiwan. With the installation of new management, and new business and technology models, business emphasis began to migrate to the more technically sophisticated networking and communications sectors that required more advanced technologies. In 2004, 100% of GUC’s revenue was at  the 0.13 µm technology node; by 2005, 5% of revenue came from the new 90 nm node and a year later, an additional 3% of revenue came from the emerging 65 nm node.

The impact of this trend was soon seen in the company finances. Revenue jumped from $20 million in 2002 to $27 million in 2003, $32 million in 2004, and a whopping $48 million in 2005—more than doubling the revenue over a four year period.

The year 2006 marked another major milestone. In the third quarter of that year, GUC became a publicly traded company when it offered its shares on the Taiwan Stock Exchange.

The operations side instituted a major focus on advanced technology. In 2007, the company developed an advanced technology digital design flow, followed shortly thereafter by a low power design flow. As a result, the company saw a large increase in the size of their designs, many with gate counts jumping exponentially. In the face of an industry-wide recession in 2009, GUC showed its confidence in the future by investing heavily in internal IP development, in particular, IP targeting the networking market segment.

This era of prosperity was reflected by a broad set of indices. Annual revenue in 2006 more than doubled that of 2005 ($48 million) at $103 million, then more than doubled again in 2007 to $216 million. In 2008, revenue jumped to $295 million before falling during the recession of 2009 to $252 million. In 2008, GUC saw a jump in revenue from advanced technology to 21 % and to 34 % in 2009, with 1 % of that coming from leading edge 40 nm products. Like all technology companies, GUC experienced a financial decline in 2009, with revenues dropping to $252 million.

But the company would rebound quickly in 2010, posting revenues of $327 million with advanced technologies accounting for 42% of that total. The year also proved auspicious. Driven by the recession to examine its business model, GUC would begin making a series of strategic decisions that would allow it to capitalize on a new era of semiconductor device design.

The company’s growth as an innovative force in the semiconductor industry is also reflected in the number of new employees required to implement increasingly complex technologies. At the end of 2003, GUC employed 132 people, most of them in Taiwan. Three years later, that number had more than doubled to 287 and by the start of 2010, the company counted 484 employees, a number that has held relatively steady through 2013. Employee growth was fueled by expanded geographic growth. GUC opened its first international office when it established a subsidiary in North America (GUC N.A.) in February of 2004 and then opened its Japan office in June of 2005. Nearly three years later, in May of 2008, the company opened its third international office, GUC Europe, in Amsterdam, The Netherlands and one month later opened an office in Korea. GUC entered the fast-growing China market when it opened an office in one of that country’s technology hubs near Shanghai in 2009.

Success in the semiconductor industry going forward is going to be heavily weighted by the ability to leverage industry’s third-party infrastructure that has now matured. Foundries are at the leading edge of the infrastructure, providing the most advanced process technologies, as well as specialized technologies to all comers. IP and chip design implementation are also being outsourced, cost-effectively utilizing technology and financial resources.

It is in this new and exciting environment that GUC evolved the Flexible ASIC Model, which is designed to provide the most effective, efficient and flexible path to semiconductor innovation.

The Flexible ASIC Model is a response to both the business and technical challenges facing today’s semiconductor companies. This model allows companies to allocate their resources more efficiently. It brings together design expertise, systems knowledge and manufacturing resources to efficiently drive delivery of the final packaged IC. The model’s basic strategy is to spread design risks and to minimize IDM, fabless and OEM (Original Equipment Manufacturers) upfront semiconductor-related fiscal and human capital investments. The goal is to increase the efficiency of the entire value chain, from concept to delivery; to shorten all phases of the development cycle; and to ultimately increase device yield quality and reliability.

At the heart of the Flexible ASIC Model is integrated manufacturing. GUC has made a strategic choice to work exclusively with TSMC, the semiconductor industry’s leading foundry service company. It is this relationship that plays an integral role in the company’s ability to achieve early advanced technology access and match designs to manufacturing resources.

Spotlight: Dr. Morris Chang

Dell changed the way personal computers are manufactured and sold. Starbucks changed the amount we would pay for a cup of coffee. eBay took the yard sale out of our yards. TSMC took the semiconductor manufacturing costs off our balance sheets and out of our capital investments.

It’s hard to overstate the impact that Dr. Morris Chang, Founder, Chairman, and until-recently CEO of TSMC, has had on the industry. He has been influential as a leader in business model innovation, and has earned his company roughly 50% of the foundry market share.

Chang left his native China in 1949, moving to the US to attend Harvard University. He soon transferred to MIT as he followed his interest in technology. After earning his MS in 1953 from MIT’s mechanical engineering graduate school, Morris went directly into the semiconductor industry at the process level with Sylvania Semiconductor and was quickly moved to management.

Chang moved to Texas Instruments in 1958, where he stayed for 25 years, rising to VP of the worldwide semiconductor business (and also earned a PhD in electrical engineering from Stanford in 1964). At TI, he worked on a four transistor project in which the manufacturing was done by IBM, thus engaging in one of the early semiconductor-foundry relationships. Also at TI, Chang developed a new model of semiconductor pricing that sacrificed early profits to gain market share and to achieve manufacturing yields that would lead to higher long-term profits.

Chang left TI in 1983 and did a short stint at General Instrument Corporation. He then moved to Taiwan to head the Industrial Technology Research Institute (ITRI), which led to the founding of TSMC.

Chang noticed in the early 1980s, while at TI and GI, that top engineers were leaving and forming their own semiconductor companies. Unfortunately, the heavy capital requirement of semiconductor manufacturing was a gating factor. The cost back then was $5-10 million to start a semiconductor company without manufacturing and $50-100 million to start a semiconductor company with manufacturing. Some of these start-ups used excess capacity from IDMs but were subjected to uncertainties in foundry capacity and sometimes had to buy wafers from a competitor. Around this time, 1985, the first truly fabless startups, like Xilinx and Chips and Technologies, were launched and doing well.

It was in 1987, within this nascent fabless environment, that Chang started TSMC. Although TSMC started two process nodes behind where semiconductor manufacturers (IDMs) were at the time, they had the advantage of being a pure-play foundry, not a competitor. Their focus was on their customers.

Morris Chang made the first TSMC sales calls with a single brochure: TSMC Core Values: Integrity, Commitment, Innovation, Partnership. Four or five years later, TSMC was only behind by one process node and the orders started pouring in. In 10 years, TSMC caught up with IDMs (except for Intel) and the fabless semiconductor industry blossomed, enabling a whole new era of semiconductor design and manufacturing. In the last 20 years, and still today, even the remaining IDMs are being forced to go fabless or fab-lite at 28 nm and below due to high costs and daunting technical challenges.

Dr. Morris Chang in 2007.

Dr. Morris Chang turned 82 on July 10th, 2013. He is still running TSMC full time as the founding Chairman. He works from 8:30 am to 6:30 pm like most TSMC employees and says that a successful company life cycle is: rapid expansion, a period of consolidation, and maturity. The same could be said about Chang himself.

2019 Update: Dr. Morris Chang

In 2017 the TSMC Museum of Innovation opened Under Fab 12 in Hsinchu Taiwan. It not only commemorates the history of semiconductors and TSMC but also the life of Dr. Morris Chang. Morris Chang’s wife Sophie was actively involved in this project:

The TSMC Museum of Innovation encompasses three exhibition galleries: “A World of Innovation,” “Unleashing Innovation,” and “Dr. Morris Chang, TSMC Founder.” Through interactive technology, digital content, and historical documents we will learn about the pervasiveness of ICs in our daily lives and about their continued advancement. In addition, we will learn how ICs are making our lives more fulfilling and how they are driving technology beyond our imagination. We will also learn how TSMC contributes to global IC innovation and to Taiwan’s economy.

In 2018 Dr. Morris Chang retired from TSMC for the second and final time:

TSMC Dr. Morris Chang Announces Retirement in June 2018. Future Dual Leadership Will Be Mark Liu as Chairman And C.C. Wei as CEO.

Issued by: TSMC Issued on: 2017/10/02

Hsinchu, Taiwan, R.O.C. – Oct. 2, 2017 – TSMC Chairman Morris Chang today announces: “I will retire from the Company immediately after the Annual Shareholders Meeting in early June, 2018. I will not be a director in the next term of the board of directors. Nor will I participate in any TSMC management activities after the Annual Shareholders Meeting in early June, 2018. From early June, 2018 on, TSMC will be under the dual leadership of Dr. Mark Liu and Dr. C.C. Wei. Dr. Mark Liu will be the Chairman of the Board, and Dr. C.C. Wei will be the Chief Executive Officer. All present directors of the board have agreed to be nominated, and if elected, serve as directors of the board during the next term. They have also agreed to support the aforementioned dual leadership of the Company under Drs. Liu and Wei. Chairman Morris Chang further said, “The past 30-odd years, during which I founded and devoted myself to TSMC, have been an extraordinarily exciting and happy phase of my life. Now, I want to reserve my remaining years for myself and my family. Mark and CC have been Co-CEO’s of the Company since 2013 and have performed outstandingly. After my retirement, with the continued supervision and support of an essentially unchanged board, and under the dual leadership of Mark and CC, I am confident that TSMC will continue to perform exceptionally.”

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400G Ethernet test chip tapes-out at 7nm from eSilicon

400G Ethernet test chip tapes-out at 7nm from eSilicon
by Tom Simon on 05-24-2019 at 10:00 am
Categories: eSilicon, FinFET, TSMC

Since the beginning of May eSilicon has announced the tape-out of three TSMC 7nm test chips. The first of these, a 7nm 400G Ethernet Gearbox/Retimer design, caught my eye and I followed up with Hugh Durdan, their vice president of strategy and products, to learn more about it. Rather than just respin their 56G SerDes, they decided to add the 112G SerDes, and at the same time use this vehicle for several other objectives. The gearbox in this chip contains 8 lanes of 56G and 4 lanes at 112G, allowing it to handle 400G Ethernet traffic. More than just showing that the SerDes work at 7nm, the configuration allows them to demonstrate a number of other things as well.

In our call, Hugh mentioned that they chose to work with Precise-ITC who develops IP for Ethernet and Optical Transport Network (OTN). They saw this as an opportunity to combine eSilicon interface IP with 3rd party IP to go through the process of integration and ensure that their StarDesigner 7nm flow was working as they expected. In essence this is a pipe cleaner of their SOC flow for 7nm.

Precise-ITC contributed a Forward Error Correction (FEC) block, Media Access Controller (MAC) and the Gearbox block. Having higher level functionality offers increased confidence in each element of the test chip. Hugh pointed out that this is a chip that customers can actually use as they evaluate the eSilicon’s offering. The chip will feature long reach and use only around 5W for the entire gearbox.

Designing at 7nm is even more difficult than at previous nodes. Lithography requirement impose many new restrictions on the layout. This makes designing chips with analog content challenging. Another aspect of the design that plays a critical role in the success of a chip like this is the packaging. Hugh told me that they used this opportunity to anticipate the complexity of designs with a much higher lane count by adding a more complex package design for some of the lanes. They also have the ability to inject noise during testing to ensure that the SerDes will perform in larger and more complex environments.

eSilicon is expecting to get silicon back in their lab by Q3 in 2019. They will make a test board that customers can use to put the SerDes and Ethernet related IP through its paces. The 112G SerDes will open the doors to continued development of Terabit Ethernet, which is becoming necessary with the explosion of data center throughput requirements.

eSilicon has consistently expended resources to stay at the leading edge of SOC technology. Their other May test chips included HBM and AI/ML designs all at 7nm. At the same time their partnerships will make life easier for their customers who are going to want to add advanced functionality to their designs. Test chips like this are a win for eSilicon, TSMC, Precise-ITC and their customers. We can eagerly await the return of silicon from this and their other test chips to learn more about how 7nm will perform in the wild. For more details, refer to the announcement on their website.