Custom SoC Platform Solutions for AI Applications at the TSMC OIP

Custom SoC Platform Solutions for AI Applications at the TSMC OIP
by Daniel Nenni on 09-27-2018 at 12:00 pm

The TSMC OIP event is next week and again it is packed with a wide range of technical presentations from TSMC, top semiconductor, EDA, and IP companies, plus long time TSMC partner and ASIC provider Open-Silicon, a SiFive Company. You can see the full agenda HERE.

AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher memory bandwidth. ASIC platforms enable AI applications through training in deep learning and high speed inter-node connectivity, by deploying high speed SerDes, a deep neural network DSP engine, and a high speed high bandwidth memory interface with High Bandwidth Memory (HBM) within a 2.5D system-in-package (SiP). Open-Silicon’s implementation of a silicon-proven ASIC platform with TSMC’s FinFET and CoWoS® technologies is centrally located within this ecosystem.

Open-Silicon’s first HBM2 IP subsystem in 16FF+ is silicon-proven at 2Gbps data rate, achieving bandwidths up to 256GBps, and being deployed in many ASICs. The data-hungry, multicore processing units needed for machine learning require even greater memory bandwidth to feed the processing cores with data. Keeping pace with the ecosystem, Open-Silicon’s next generation HBM2 IP subsystem is ahead of the curve with 2.4Gbps in 16FFC, achieving bandwidths up to >300GBps.

This 7nm ASIC platform is based on a PPA-optimized HBM2 IP subsystem supporting 3.2Gbps and beyond data rates, achieving bandwidths up to >400GBps. It supports JEDEC HBM2.x and includes a combo PHY that will support both JEDEC standard HBM2 and non-JEDEC standard low latency HBM. High speed SerDes IP subsystems (112G and 56G SerDes) enable extremely high port density for switching and routing applications, and high bandwidth inter-node connections in deep learning and networking applications. The DSP subsystem is responsible for detecting and classifying camera images in real time. Video frames or images are captured in real time and stored in HBM, then processed and classified by the DSP subsystem using the pre-trained DNN network.

Implementation challenges for AI ASICs include design methodologies for advanced FinFET nodes, physical design of large ASIC >300 mm2 running at GHz speed, power and timing closure, system level power and thermal and timing signoff. Open-Silicon has overcome these challenges with advanced implementation strategies that enable Advanced On-Chip Variations (AOCV) flow for physical design and timing closure, correlation between implementation and signoff that results in faster design convergence, an advance node power plan and validation techniques, and system level signal and power integrity signoff for a complete 2.5D SiP. Additionally, various in-house development tools help debug and analyse the design data through physical design phases, thus speeding convergence of complex designs.

Open-Silicon’s DFT methodology enables the test and debug challenges in large ASIC designs by incorporating methods such as core wrappers, hierarchical BIST/scan, compression, memory repair, power aware ATPG and enablement of wafer probing to ensure quality KGD before 2.5D assembly, interconnect test between ASIC and HBM, and incorporating design practices recommended by TSMC CoWoS® to improve 2.5D SiP manufacturing and yield.

Open-Silicon’s ASIC design and test methodology, low area high performance HBM2 IP subsystem, and its experience in high speed SerDes integration and DSP subsystem implementation, offer best-in-class custom silicon solutions for next generation AI and high performance networking applications.

Who: Bhupesh Dasila, Engineering Manager – Silicon Engineering group, Open-Silicon
What: Custom SoC Platform with IP Subsystems Optimized for FinFET Technologies Enabling AI Applications
When: Wednesday, October 3 2018, 1:00 pm
Where: EDA/IP/Services Track, Santa Clara Convention Center

Open-Silicon is exhibiting at Booth, #907

The TSMC Open Innovation Platform®
(OIP) Ecosystem Forum is a one-of-a-kind event that brings together the semiconductor design chain community and approximately 1,000 director-level and above TSMC customer executives. The OIP Forum features a day-long, three-track technical conference along with an Ecosystem Pavilion that hosts up to 80 member companies.


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where timing and power closure will work regardless. Such an issue would only be uncovered during final SPICE netlist checks. Another potential problem could include a case where LEF does not match GDS, completely slipping through the cracks, through full synthesis, and would only be caught during chip level DRC or LVS. This would ultimately require updates to the IP as well as re-synthesis (more slippage).

How can one avoid these potential problems? Simple, with Fractal’s Crossfire QA suite. Fractal is your specialized partner for IP qualification. Crossfire can help you deal with design view complexities, increasing amount of checks required to correctly QA an IP, and the difficulties of dealing with excessive volumes of data.

Crossfire supports over 30 standard design formats, from front-end to back-end, including simulation and schematic views, binary databases such as Milkyway, OpenAccess, and NDM, documentation, and custom formats such as Logic Vision and Ansys APL. Any other ASCII based custom formats can also be easily integrated into the tool.

Getting back to the scope of this article, the recommended baseline of checks can be separated into three sections: cell and pin presence for all formats, back-end checks, and front-end related checks.

Cell and Pin Presence Checks
Although consistency checks such as cell and pin presence may sound trivial, and for the most part, they are, one cannot sweep such an important task under the rug. Don’t be surprised if an IP or standard cell library from a well-known IP vendor is delivered with inconsistencies between the various formats, including cell and pins names, port direction, and hierarchy differences.

Back-end Checks
Ensuring layout related consistencies across all back-end related formats is an important part of the IP QA qualification. Pin labels and shape layers must match across all layout and abstract formats. All layout formats such as GDS, Oasis, Milkyway CEL, NDM and OpenAccess layout views must directly match across the board. When comparing a layout to an abstract format such as LEF, Milkyway FRAM or NDM frame, one must ensure that all layer blockages correctly cover un-routable areas in the layout. On top of that, pin shapes and layers must match in order to guarantee a clean DRC/LVS verification down the line.

Other important checks to consider include area attribute definitions for non-layout formats which must match the area defined by the boundary layers for various layout formats. IP and standard cell pins must be accessible by the router and for non-standard cell related IP, pin obstruction needs to be checked in order to ensure accessibility. In some cases, ensuring that all pins are on a pre-defined grid can also be a necessary task. In the end, these checks will ensure a quicker and less error-prone P&R execution.

Front-end Checks
Front-end checks can be broken into seven separate sections: timing arc, NLDM, CCS, ESCM/EM, NLPM, functional characterization, and functional verification. In this blog, we’ll be covering the latter two related to functional checks. The first five sections related to characterization deserve an article all on their own, therefore, they will be covered in an upcoming blog.

Functional characterization checks ensure the timing arcs are defined correctly when compared the given Boolean functions for formats like Liberty, Verilog, and VHDL. Other checks include power down function correctness, ensuring related power and ground pins are defined correctly when compared to spice netlists or UPF models (correct pins are extracted from spice by traversing the circuits defined in the spice format). We also recommend checking related bias pins and whether input pins are correctly connected to gate or antenna diodes.

When dealing with standard cell libraries, it is important to establish the Boolean equivalence of all formats that describe the behavior of a cell. This will ensure that all formats behave in the same manner when dealing with functionality during various front-end related timing simulations.

What else can Crossfire do?
Crossfire is technology independent. From a tool perspective, the differences include:

  • Exponential data size growth (up to 2x when compared to previous node)
  • Introduction of new design formats (i.e. NDM)
  • Number of corners increasing drastically in newer nodes (i.e. FinFet based)

As a tool, Crossfire only has to differentiate between standard cell libraries and all other IP (memories, digital, analog, mixed-signal, etc.). Some checks, such as abutment or functional verification, are designed specifically for standard cell libraries.

Crossfire is a proven validation tool used by various Tier 1 customers. All checks and formats supported by Crossfire are based upon direct cooperation with our customers. Customers moving from “old” to “new” technology nodes automatically get all the checks and format support developed for and used by Tier 1 customers. This cycle of shared knowledge is passed on from one technology node to another.

Conclusion
IP qualification is an essential part of any IC design flow. A correct-by-construction approach is needed since fixing a few bugs close to tapeout is a recipe for disaster. Given that, IP designers need a dedicated partner for QA solutions that ensures the QA needs of the latest process nodes are always up-to-date. In-house QA expertise increases productivity when integrated with Crossfire. All framework, parsing, reporting, and performance optimization is handled by the tool. On top of that, with a given list of recommended baseline checks, we ensure that all customers use the same minimum standard of IP validation for all designs.

TSMC OIP
The Crossfire team and I will be at a booth in the TSMC OIP exhibit hall next week giving out free copies of our Fabless book, discussing the need for IP qualification, and demonstrating the latest Crossfire software. I hope to see you there!


UMC and GF or Samsung and GF?

UMC and GF or Samsung and GF?
by Daniel Nenni on 09-17-2018 at 7:00 am

One of the interesting rumors in Taiwan last week was the possibility that UMC and GF will do a deal to merge or UMC will buy some GF fabs. I have talked to quite a few industry experts about it and will talk to more this week at the GSA US Executive Forum (more at the end). The US Executive Forum is what they call a C Level event which means it is invitation only and expensive.

This year’s program looks very good. Notice the heavy AI emphasis, as I have said many times before AI will touch most every chip and will keep pushing the leading edge processes, absolutely. EDA CEOs Wally Rhines and Aart de Geus will be there. Wally does a great “Industry Vision” loaded with facts and figures and Aart is not afraid to ask the difficult questions on his panel so both of these talks should be interesting.

Keynote: Looking To The Future While Learning From The Past, Daniel Niles / Founding Partner / AlphaOne Capital Partners

Keynote: Convergence of AI Driven Disruption: How multiple digital disruptions are changing the face of business decisions, Anthony Scriffignano / Senior Vice President & Chief Data Scientist / Dun & Bradstreet

Significance of AI in the Digitally Transformed Future
This session will discuss how developments in machine learning, deep learning and AI are impacting technology segments and market verticals and the significance of Artificial Intelligence in the Digitally Transformed Future.

AI and the Domain Specific Architecture Revolution
Wally Rhines / President and CEO / Mentor, a Siemens Business

AI Driven Security
Steven L. Grobman / Senior Vice President and CTO / McAfee

Innovating for AI in Semis and Systems

AI Accelerators in the Datacenter Ecosystem
Kushagra Vaid / General Manager & Distinguished Engineer – Azure Infrastructure / Microsoft

Delivering on the promise of AI for all – from the data center to the edge of cloud
Derek Meyer / CEO / Wave Computing

Driving the Evolution of AI at the Network Edge
Remi El-Ouazzane/Vice President and COO, Artificial Intelligence Products Group / Intel

The Physics of AI: Architecting AI systems into the Future
Sumit Gupta / Vice President AI, ML and HPC / IBM

AI Panel Discussion
The panel will discuss the innovations in the semiconductor and systems space that are empowering Artificial Intelligence and the collaboration opportunities between semiconductor and systems players to enable emerging markets.

Moderator:
Aart de Geus / Chairman and Co-CEO / Synopsys

Panelists:
Derek Meyer
Sumit Gupta
Kushagra Vaid
– Remi El-Ouazzane

Keynote: Long Term Implications of AI & ML
Byron Reese / CEO, Gigaom / Technology Futurist / Author

VIP Reception
Book signing by Byron Reese
The Fourth Age: Smart Robots, Conscious Computers, and the Future of Humanity

Back to the UMC GF Samsung rumor. Remember, GF has built-out fabs in Singapore, the US, and Europe. GF also has the IBM patents and technology plus the ASIC group which has been spun out. Think about UMC’s pros and cons and see if they match up to GF’s assets and keep in mind, whatever UMC does not need Samsung may want. The ASIC business for example (UMC has Faraday). It would also give GF’s owner a somewhat graceful exit from the semiconductor industry. If you combine UMC and GF it gets you a $5B pure-play foundry which is much closer to TSMC’s $15B.

Of course Samsung could just buy GF outright so there is always that. Just a rumor of course but not unlike the “GF buys IBM semiconductor” rumor we started a while back: GLOBALFOUNDRIES Acquires IBM Semiconductor Unit!


2018 Semiconductor Winners and Losers

2018 Semiconductor Winners and Losers
by Daniel Nenni on 09-12-2018 at 7:00 am

This is an ongoing conversation inside the semiconductor ecosystem, especially when I am traveling. Everyone wants to know what is going on here or there and since I just returned from Taiwan I will post my thoughts. Last week was also my birthday which was cut short due to the time change but I did get preferential treatment on the flight and at the hotel. Upgrades, champagne, treats, and a full-fledged cake from Hotel Royal in Hsinchu. Either I haven’t traveled on my birthday before or they didn’t roll out the red carpet last time or I would have remembered this, absolutely.

My choice for #1 winner is of course TSMC. They are having a great year and will continue to do so, my opinion. GF ending 7nm put AMD firmly in place at TSMC, Intel is rumored to be moving more products to TSMC, and of course Apple and the rest of the industry has already taped-out to TSMC 7nm so get the marching bands and the dragon dance ready for the end of year celebration.

One note about the Intel move, it is being reported that processors (Coffee Lake) are being moved to TSMC. I find this highly unlikely. Intel 14nm is in no way compatible to any TSMC process so this would be a redesign and why would Intel do that? It is much more likely that mobile chips would be retargeted for TSMC (SoCs, modems, IoT, etc…). Remember, the Intel Silicon Engineering Group is now run by Jim Keller. Jim was at Apple, AMD, and Tesla before Intel so he knows TSMC. Maybe even the next generation FPGAs since Intel is going to be short on 10nm and the ex Altera folks are very TSMC experienced. Or maybe the GPUs since TSMC is very good at GPUs (NVIDIA). There is a forum thread on this you may want to take a look at: Intel 14nm capacity issue.

Broadcom is another winner. Hock Tan keeps changing the rules of the semiconductor game and there is no telling what he will do next but you can bet it will be disruptive. We all scratched our heads when Broadcom acquired Computer Associates for $18.9B in cash. Hock clarified his strategy in the quarterly call:

Speaking of acquisitions, before I turn this call back to Tom to talk about the financials in greater detail, let me perhaps take a few more minutes and talk about CA Technologies. The number one question we get from when we get with CA is, why did we choose to buy? Cut to the chase. We’re buying CA because of the customers and their importance to these customers. CA sales mission critical software to virtually all of the world’s largest enterprises. These are global leaders in key verticals including financial services, telecoms, insurance, healthcare and retail. And CA does it a scale fairly unique to the infrastructure software space. This can only come from longstanding relationships with these customers that spend several decades. In other words, these guys are deeply embedded… https://www.legacy.semiwiki.com/forum/f302/interesting-notes-broadcom-q3-2018-call-10764.html

I also consider GF a winner with their new boutique foundry pivot. I covered this in a previous post GLOBALFOUNDRIES Pivoting away from Bleeding Edge Technologies.

For losers I would start with Intel. 10nm is still in question and even more loserish is the way they disposed of their CEO who spent his entire career at Intel. I cannot believe a Silicon Valley icon like Intel would do such a despicable thing to a 36 year veteran. Clearly it was sleight of hand, waving one hand so you do not see what the other is doing, or not doing in this case. Replacing a questionable CEO with a temp CEO who has publicly declared he does not want to be CEO while you spend months looking for a new CEO? The big question I have is: Why is the Intel Board of Directors NOT being held accountable for this blunder?Correct me if I’m wrong here but this does not pass the corporate smell test.

Let’s continue this discussion in the comments section. Who do you think the semiconductor winners and loser of 2018 will be?


TSMC GlobalFoundries and Samsung Updates from 55DAC

TSMC GlobalFoundries and Samsung Updates from 55DAC
by Daniel Nenni on 08-20-2018 at 7:00 am

One of my favorite traditions at the Design Automation Conference is the Synopsys foundry events (the videos are now available). I learned a long time ago that the foundries are the foundation of the fabless semiconductor ecosystem and your relationships with the foundries can make or break you, absolutely. I also appreciate the free food, food tastes much better when it’s free.

Synopsys has an advantage being not only the number one EDA company but also the number one IP provider with the largest IP portfolio known to semiconductor man or woman. You can bet Synopsys tools and IP are silicon proven on every edge of the process technology spectrum (leading through trailing) without a doubt. One of the benefits of live events of course is that you get to mingle with the crowd and speakers which includes ecosystem executives from all over the world and don’t be surprised if Aart de Geus or Chi-Foon Chan are breaking bread at your table.

My favorite breakfast of course is the one with my semiconductor bellwether TSMC. Willy Chen, Deputy Director, Design Methodology and Service Marketing, TSMC, is a great speaker and very transparent in what he presented last year versus this year. Willy is a very smart and fashionable guy and very approachable so approach him if the opportunity presents itself. Kelvin Low (Moderator), VP of Marketing, Physical Design Group, Arm is also a great speaker. Kelvin spent the first half of his career with foundries (Chartered, GF, and Samsung) and is now IP. Hopefully next he will go into EDA completing the ecosystem trifecta! Also speaking were Kiran Burli, Director, Solutions Marketing, PDG, Arm and Joe Walston, Principal Engineer, Synopsys.

Designing with Leading-Edge Process Technology, CPU Cores and Tools
Faster, smaller, cooler product requirements continue to challenge designers to achieve their targets. TSMC, Arm and Synopsys kicked off DAC 2018 to share results of their collaboration to address these challenges to enable optimized design and accelerate design closure for Arm®-based designs on the latest TSMC process technology using the Synopsys Design Platform. This event video introduces the new Synopsys QuickStart Implementation Kits (QIKs) for ARM® Cortex®-A76 and Cortex-A55 processors that take advantage of ARM POP™ technology and Synopsys tools, and the collaborative design enablement for TSMC 7-nm process technology.

My beautiful wife joined me for the GlobalFoundries dinner which was focused on FD-SOI. As you know I am a big fan of FD-SOI which we track closely on SemiWiki. In fact, Scotten Jones just did a very nice FDSOI Status and Roadmap last month following SEMICON West. Kripa Venkatachalam, Director of Product Management, GLOBALFOUNDRIES, did a very nice presentation followed by Wayne Dai, President and CEO, VeriSilicon, and Jacob Avidan, SVP of Design Group R&D, Synopsys.

Addressing the Design Challenges of IoT Wearables and Automotive with 22FDX Technology
In this video of the Synopsys and GLOBALFOUNDRIES dinner panel event at DAC 2018, you will hear a discussion of how GLOBALFOUNDRIES’ innovative FDX process coupled with Synopsys’ design tools are providing mobile, IoT and automotive chip designers with the low-power and high-performance technology required for product success. VeriSilicon shared some specific examples of their successes with GLOBALFOUNDRIES’ 22FDX process and Synopsys tools. The event concluded with a panel discussion on various aspects of designing with 22FDX and addressing barriers to adoption of this technology.

Last but not least was the Samsung breakfast featuring Robert J. Stear, Senior Director, Samsung Foundry; JC Lin, Vice President of R&D, Synopsys; and John Koeter, Vice President of Marketing, Synopsys. Samsung has made great ecosystem strides in the past few years and is clearly experiencing the benefits. In fact, Samsung is holding a Tech Day on October 17[SUP]th[/SUP] in San Jose. If you have a golden ticket I hope to see you there. Tom Dillinger and I will be covering it for SemiWiki.

EUV is a very hot topic and Samsung is leading the way with their 7nm EUV process. Scott Jones has also covered Samsung and EUV with Samsung 10nm 8nm and 7nm at VLSIT and SEMICON West – Leading Edge Lithography and EUV
Enabling Optimal Design with Samsung 7nm EUV Process Using the Synopsys Design Platform
As each new process technology brings with it significant advantages as well as design challenges, Samsung Foundry and Synopsys continue to collaborate to enable optimal design. At this event, you’ll learn how our efforts provide a robust foundation for designers to get the most from Samsung advanced process technologies using Synopsys’ Design Platform with Fusion Technology and state of the art IP.

Take a look at the videos and let’s talk foundries in the comment section…


AMAT down 10% as expected Foundry spending slow down unexpected

AMAT down 10% as expected Foundry spending slow down unexpected
by Robert Maire on 08-19-2018 at 12:00 pm

Applied reported a more or less in line quarter, slightly beating weaker expectations. As we had projected, the October quarter is expected to have revenues down 10% which is at the low end of our expected 10-15% drop in business. Applied services helped partially make up for some of the equipment sales weakness. Revenue came in at $4.47B versus street of $4.43B and EPS was $1.20 versus street $1.17. The October quarter is guided to $4B and EPS of $0.96 versus $4.46B and $1.17. Its clear that most analysts neglected to cut their numbers despite the widespread news.

Similar to what we heard from both Lam and KLA, management suggested Sept/Oct quarter would be a trough. However we were slightly surprised that management refrained from describing what the recovery might look like, and how long we would be in the trough. This is a sharp variation from KLAC which called for a “sharp snapback” and even weaker than Lam’s vague and softer, “positive trajectory” comments.

Perhaps one of the reasons for the weaker and less committed outlook is that Applied revealed on the call that the weakness in spending which had been limited to Samsungs memory side has now spread to foundry customers. Thats customers with an “S” as in more than one foundry is slowing down their spending.

We can only assume that both TSMC and Samsung are slowing their foundry spend as they are the biggest foundries and GloFo isn’t spending that much to start with. This seems to be somewhat confirmed as the mix of foundry business has been shifting from leading edge to trailing edge spend. The company still feels very bullish about 2019 being up in spend but we think its going to be very hard to get there from here if both memory at Samsung and at least two foundry customers are slowing their spend.

Its also clear that there is not an expectation of a rescue coming in from the display side of the business. The part of the business that’s doing a great job continues to be Applied’s services business which is helping to offset weakness in new tool sales. It’s clear to us that the reduced cyclicality is as much a reflection of a higher services business as it is a reflection of more rational spending

Potential share loss???
In doing the math of AMATs tool business against global WFE spend is seems as if AMAT is losing share as its revenue, as quoted on the call, is not growing as fast as the industry top line. Management danced around without directly answering a question on the call on the share loss math. This could be due to the predominance of memory spending we have seen where AMAT has a lower share.

2019 Outlook

Management doubled down on their outlook for 2019 by saying that 2018 and 2019 will now exceed $100B where they had previously just said $100B. If the October and January quarters are weak in 2018 we can see how 2019 could be better but we are more dubious of what will now have to be higher growth in 2019 to make the numbers work, especially in light of BOTH memory and foundry being weaker.

Handset Weakness?
We had previously mentioned our concern about Samsung’s potential plan to shutter a China handset factory. We think this could be evidence of further slowing which manifested itself as a slow down in foundry spend at both TSMC and Samsung that would obviously have been making chips for the factory that is to be shut.

The Stock
Investors obviously did not like the lower outlook and the spread of weakness to now include foundrieS, as the stock was off over 4% in the after market. We would imagine that this new, added concern about foundry spending will likely weigh on the group as a whole tomorrow. We had also been hoping for a stronger rebound statement that would show some hard evidence or confidence in the speed of some sort of recovery but that was also missing on the call. Applied results coupled with less than stellar news out of Nvidia could spread to other semi names and we could see the overall group weaker as well.

Also Read: Chip Stocks have been Choppy but China may return


Keeping Pace With 5nm Heartbeat

Keeping Pace With 5nm Heartbeat
by Alex Tan on 07-23-2018 at 12:00 pm

A Phase-Locked Loop (PLL) gives design a heartbeat. Despite its minute footprint, it has many purposes such as being part of the clock generation circuits, on-chip digital temperature sensor, process control monitoring in the scribe-line or as baseline circuitry to facilitate an effective measurement of the design’s power delivery network (PDN).
Continue reading “Keeping Pace With 5nm Heartbeat”


Morris Chang and Me

Morris Chang and Me
by Sunit Rikhi on 07-04-2018 at 12:00 pm

Legend has it that in 1984, Morris Chang was approached by a friend who was looking for money to buy equipment for manufacturing his electronic chip designs. Morris told him to do more homework. When his friend did not return, Morris reached out to him. His friend, it turned out, did not need the money after all. He had found another manufacturer willing to “rent” him equipment capacity at a fraction of the cost.

Morris was intrigued. Moore’s Law was two decades strong, delivering faster, cheaper, and cooler transistors every couple years. More and more chip designers were designing innovative products with these transistors, pushing up the demand for manufacturing. Like his friend, not all chip designers could afford their own manufacturing capacity. Was the world ready for semiconductor manufacturing services?

It took Morris 3 years to answer that question. By 1987, he had launched Taiwan Semiconductor Manufacturing Corporation (TSMC) – a company that manufactured chips for others, as a service. The company is known as a foundry because of the similarity of its business model with that of metal casting foundries in operation since early 19th centur

I never met Morris Chang. But, for the three decades that followed, I was his fellow traveler, a keen observer, a student, and a competitor.

Back in 1984, I was a 27 year old electronics engineer starting my career with Intel. Intel was (and still is) an Integrated Device Manufacturer (IDM). The IDM business model is the opposite of the foundry business model. An IDM develops manufacturing capability for its own products designed by its own IC designers. A foundry on the other hand, develops manufacturing capability for its customers’ products designed by its customers’ IC designers. A foundry helps its customers compete with IDMs.

Intel and TSMC grew up as leaders in the semiconductor industry they helped shape. Both drove exponentials: one in the electronics capability world-wide, and another in the reduction of cost for that capability. It resulted in fundamental changes in the way we live.

For most of this period, the industry generally accepted Intel as the leader at the edge of Moore’s Law, by at least a generation. I was one of the Intel voices shining light on Intel’s lead and explaining how that lead gives a competitive edge to Intel’s chips. Publicly, Morris did not indulge much in the technology leadership question, choosing instead to emphasize TSMC’s brand promise of customer service, trustworthiness and breadth of offerings.

In a 1998 interview, Morris said “The main thing that we’ve learned is that foundry is a service-oriented business, so we are molding ourselves into a service company”. These words were not from a business school slide. They came from deep and powerful insights of a master business man. They captured the pith of TSMC’s winning strategy. An important aspect of the service strategy was the harvesting of immense knowledge from the intimate teamwork between TSMC technologists and its customers’ IC designers. The willingness to learn from his customers was crucial in targeting and tuning his offerings to match his customers’ needs.

His emphasis on customer service did not mean TSMC was not focused on advancing with Moore’s Law. It was. I once described this pursuit as a group led by Intel, running towards an invisible wall, on an increasingly difficult terrain, and in a fog that was getting denser by the year. During this journey, Intel could hear the sounds of rival footsteps behind it, with many growing fainter over time. But not TSMC’s. It had been consistent, even getting louder, as it pulled up to Intel and started running shoulder to shoulder. Morris was clear about the importance of technology in making his customers competitive. In one interview he said “TSMC will stand behind our customers and cooperate with them. The battlefield between our customers and Intel is where we compete against Intel”.

The dawn of this century saw a change in client computing landscape. By then, the computer had spread from the desktop to the lap, but the move to the pocket was just starting. Intel assumed that Intel Architecture would sail into the pocket as easily as it did into the laptop. History however, proved that assumption wrong. The late Paul Otellini, Intel’s CEO at the time, considered that as one of his most significant failures. It was, in fact, Intel’s failure, not just his own. We at Intel felt entitled to success in markets where we were not incumbents. Our actions and inactions were rooted in that. But this was one of TSMC’s most spectacular successes, a result of years of customer-driven learning and delivering to commitments.

By 2008, Intel had launched a foundry division called Intel Custom Foundry (ICF), aiming to manufacture custom products for strategic customers. Intel was not the first to think of creating a foundry within an IDM. IBM offered foundry services long before that, and so did Samsung. However, due to Intel’s reputation as the leader in pursuit of Moore’s Law, even the most skeptical potential customers were intrigued, despite their concerns about incompatibility between the foundry and the IDM models. With ICF, Intel competed directly with TSMC. I led the formation and build up of ICF.

Soon, I came face to face with TSMC on the battlefield. In 2013, Altera Corp decided to switch from TSMC to Intel for their leading edge chips. Although Altera was not one of the highest revenue customers of TSMC, it was a strategic customer because it drove the leading edge of Moore’s Law. At the Q1 2013 TSMC earnings call, Morris was asked questions about the design loss of Altera. He said that he hates to lose even a part of an old customer. He said he regretted the loss and because of this, TSMC had investigated and thoroughly critiqued itself. He continued “..and there were, in fact, many reasons why it happened and we have taken them to heart. It’s a lesson to us and at least, we’ll try our very best not to let similar things happen again”. He clearly held himself accountable for the loss and resolved to do something about it. His humility was admirable and disarming. It kept me from gloating over my win.

Morris Chang was 55 when he started TSMC, and he walked away earlier this month, ending his glorious innings at age 86. This transformational giant of the semiconductor industry taught us through his goal clarity, personal humility, and tenacious stamina, that inspiration can hit at any age, and spectacular climbs to unimagined peaks can be undertaken anytime. Thank you, Morris.


7nm, 5nm and 3nm Logic, current and projected processes

7nm, 5nm and 3nm Logic, current and projected processes
by Scotten Jones on 06-25-2018 at 7:00 am

There has been a lot of new information available about the leading-edge logic processes lately. Papers from IEDM in December 2017, VLSIT this month, the TSMC and Samsung Foundry forums, etc. have all filled in a lot of information. In this article I will summarize what is currently known.
Continue reading “7nm, 5nm and 3nm Logic, current and projected processes”


TSMC OIP DAC Theater Schedule 2018

TSMC OIP DAC Theater Schedule 2018
by Daniel Nenni on 06-20-2018 at 6:00 am

The TSMC OIP DAC Theater schedule is finalized and ready to go. It kicks off Monday at 10:15 am in booth #1629 and ends with a raffle at 5:45 pm each day (Mon-Tue-Wed) TSMC gives out some very nice prizes so check in with the TSMC booth staff when you arrive. There are 66 coveted presentation spots representing the top ecosystem partners around the world. The TSMC theater is one of the busiest and if you look at the attached schedule you will see why.

TSMC OIP DAC:
Overview Schedule Raffle

Honorable mentions go to the presentations by companies that we work with:

  • Analog Bits: A Case Study of FinFet SERDES for AI
  • ANSYS: ADAS Reliability for Advanced FinFET Design
  • Cadence: Virtuoso Design Platform for Advanced Nodes
  • Cadence: Advanced Semiconductor Packaging
  • Cadence: IP Solutions for Advanced Nodes
  • Cadence: High Performance 7nm Digital Design
  • Flex Logix: Applications and Value Proposition of eFPGA by Market
  • Moortec: FinFET Optimization and Reliability Enhancement
  • Mentor: Verification Solutions for TSMC Advanced Packaging
  • Mentor: Verification and Advanced DRC
  • Mentor: Tessenet DFT Yield Solutions for Advanced Nodes
  • SiFive: Enabling Access to Silicon
  • Silicon Creations: High Performance PLL Design on 5nm FinFET
  • Silvaco: Technology Behind the Chip
  • Synopsys: Silicon Proven Designware IP for TSMC Processes
  • Synopsys: Power ECOs with ANSYS Redhawk
  • Synopsys: Custom Platform for TSMC
  • TSMC OIP Update

Special mention goes to Open Silicon who sent abstracts for their TSMC theater presentations:

Topic: Turnkey 2.5D HBM2 ASIC SiP Solution for Deep Learning and Networking Applications
Presenter: Asim Salim / VP of Manufacturing Operations, Open-Silicon

The most common memory requirements for emerging deep learning and networking applications are high bandwidth and density, based on real-time random operations. High Bandwidth Memory (HBM2) meets these requirements and delivers unprecedented bandwidth, power efficiency and small form factor. Open-Silicon’s silicon proven HBM2 IP subsystem in TSMC’s FinFET and CoWoS® technologies is enabling next generation high bandwidth applications and the successful ramping of 2.5D HBM2 ASIC SiP designs into volume production.

Topic:IP Subsystem solutions for Deep Learning and Networking Applications
Presenter: Kalpesh Sanghvi / Technical Manager of IP and Platforms, Open-Silicon

For Deep Learning and Networking applications ASICs, HBM IP Subsystem, Networking IP Subsystem are main building blocks. Open-Silicon’s first HBM2 IP subsystem in 16FF+ is silicon-proven at 2Gbps data rate, achieving bandwidths up to 256GBps. Open-Silicon’s next generation HBM2 IP subsystem supports 2.4Gbps in 16FFC, achieving bandwidths up to >300GBps and supports 3.2Gbps and beyond data rates in 7nm, achieving bandwidths up to >400GBps. Open-Silicon’s Networking IP subsystem includes high-speed chip-to-chip interface Interlaken IP, Ethernet Physical Coding Sublayer (PCS) IP, FlexE IP compliant to OIF Flex Ethernet standard v1.0 and v2.0, and Multi-Channel Multi-Rate Forward Error Correction (MCMR FEC) IP.

Topic:Package Design, Assembly and Test Strategies for Robust 2.5D HBM2 ASIC SiP Manufacturing
Presenter: Abu Eghan / Sr. Manager of Packaging & Assembly, Operations, Open-Silicon

2.5D HBM2 ASIC SiPs manufacturing has unique challenges for package design, assembly and testing both at the wafer level and the SiP level. Open-Silicon’s has proven solutions and strategies that are available to mitigate these issues in order to successfully ramp ASIC SiP designs into volume production.

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM SIGDA), the Electronic Systems Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineer’s Council on Electronic Design Automation (IEEE CEDA).