Adding sophisticated 2D dynamic compaction technology to address 20nm and 14nm challenges. Santa Clara, California – May 3 ,2012 – Sagantec today announced that it has acquired Dutch startup NP-Komplete Technologies BV (Eindhoven, The Netherlands) for its physical design compaction and migration solutions based on a sophisticated… Read More


San Francisco Bars
If you are visiting DAC and want a drink in the evening then you are in an interesting city and you don’t have to go to a bar just like the ones in the city where you live. Here are a few unique places but take note, most of these places don’t serve any food, they are all about the drinks:
Bourbon and Branch. It is an old speakeasy. You … Read More
Is PHY IP really strategic? Just take a look at the various legal offensives running these days…
Last week, at the same time I was writing a blog about PHY IP market, claiming that this market was shaken, several events happened – not on the pure business side, but on the legal side. This means that I will have to carefully check before using each word of this blog!
If you remember, the blog conclusion was focusing on V Semiconductor,… Read More
Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP
Synopsys is consolidating the company positioning on Verification IP. We have announced the launch of Discovery VIP in Semiwiki, in February this year, and we have commented about the acquisition of nSys and ExpertIO in January. This webinar, “Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™… Read More
TSMC 20nm Challenges!
Now that the 28nm challenges are dead
It is time to look ahead
The tabloid pundits may not agree
But Moore’s law again you will see
The semiconductor ecosystem is humming
(2X gate density -20%+ performance-20%+ power savings)
The 20nm design starts are coming!
Okay, I’m really bad at poetry. Gambling however, I do pretty well. Las… Read More
Formal Verification, there’s an App for that
The success of Apple’s AppStore has made people aware that software doesn’t have to be delivered in a big monolithic lump. Indeed, going back a bit earlier, Apple’s iTunes store made people aware that you didn’t have to buy a whole album if you only wanted a track or two.
EDA applications in today’s… Read More
Where to eat lunch or get a beer at DAC
You are going to DAC. And you don’t want to eat a Moscone Center rubber chicken Caesar salad for lunch. But you lack local knowledge. So here are some places within a 10 minute walk. These are just places I like. Nobody is paying me to recommend them.
Places to eat
The food court in the San Francisco Center on Market Street between… Read More
GlobalFoundries 2012 Update!
What’s new with Glofo? Quite a bit actually. It was interesting to see a Made in America: Global Companies Expand in U.S. Towns segment on semiconductors! Give it a look, I enjoyed it. It’s an election year, jobs are key to any election, so it did not surprise me to see President Obama making the rounds:… Read More
It is free after you pay for it and there is a one-time annual fee: The Case for FD-SOI
In one of Portlandia’s TV program sketches, there is a funny interchange between a carrier salesperson and Fred Armisen (of SNL fame) who was trying to buy a phone. One chuckle line was a statement by the seller that the phone was free after paying for it and that there was a one-time annual fee. With this anecdote as a mental backdrop,… Read More
28nm Layout Needs Signoff Quality at Design Time
We are all aware that at 28nm and below several types of complex layout effects manifest themselves into the design and pose a herculean task, with several re-spins to correct them at pre-tapeout. It’s apparent that the layout needs to be correct by construction at the very beginning during the design stage.
A Quick Tour Through Prompt Engineering as it Might Apply to Debug