The RISC-V and Open-Source Functional Verification ChallengeMost of the RISC-V action at the end…Read More
Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers2.5D package design is rapidly finding its stride…Read More
Addressing Reliability and Safety of Power Modules for Electric VehiclesAs electric vehicles (EVs) gain widespread adoption, safety,…Read More
Shaping Tomorrow’s Semiconductor Technology IEDM 2024Anyone who has read my articles about IEDM…Read More
SI and PI Update from Cadence on Sigrity XSignal Integrity (SI) and Power Integrity (PI) issues…Read More
EDAC (EDA consortium) market statistics service announced the data for Q3 of 2011. Revenue increased 18.1% (versus 2010) to $1543.9 million. Sequentially (versus Q2) revenue increase 7.4%. Annualized, that puts EDA at over $6B for, I belive, the first time ever. Wally Rhines, who is EDAC chair (and CEO of Mentor) commented that… Read More
Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.
To meet these new requirements for performance and power, memory… Read More
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More
As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More
One of the most significant announcements at the consumer electronics show (CES) this week was Intel’s Medfield, an Atom-based smartphone SoC. The SoC itself is unremarkable, perhaps a little better than ARM Cortex-based SoCs in some areas, worse in others. The reason it is significant is that Motorola (soon to be Google,… Read More
Virtual fabric sounds like something that would be good for making the emperor’s new clothes. I talked today to Les Spruiell of Imera to find out what it really is.
Anyone who has worked as either a designer or as an EDA engineer has had the problem of a customer who has a problem but can’t send you the design since it is (a)… Read More
The might have beens. The shoulda’s, coulda’s, woulda’s are what launches a thousand Harvard Business School Case Studies that are meant to prepare a generation of business leaders on how to make decisions that impact the future directions of companies. Right before the 2008 financial crises (September … Read More
Mostly I blog about EDA software however the end objective of IC design is to produce an electronic system like the Kindle Touch, a popular e-book reader from Amazon introduced in late 2011.
Tear Down
This particular model has the following components (Source: Tech Republic):
The big challenge with audio is that there are so many standards. Some of this is for historical reasons since audio for mobile (such as mp3), for the home (Dolby 5.1) and for cell-phone voice encoding/decoding have all had very different requirements, different standard setters and so on. But gradually everything is coming together.… Read More
Synopsys was started in 1986 and so 2011 was its 25th anniversary. They created a little timeline with some of their history. As with most companies, the earlier history is the most interesting, before it was clear what the future would bring. From 1986 to 1990 they grew to $22M in revenue, which was explosive growth. So explosive … Read More
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