Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping SystemQualifying an AI-class RISC-V SoC demands proving that…Read More
DAC News – A New Era of Electronic Design Begins with Siemens EDA AIAI is the centerpiece of DAC this year.…Read More
Arteris at the 2025 Design Automation Conference #62DACKey Takeaways: Expanded Multi-Die Solution: Arteris showcases its…Read More
Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.
In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:… Read More
A few years ago I was having breakfast with Jim Hogan at our favorite place to meet in Los Gatos. I was CEO of Polyteda and Jim was Chairman so we always had plenty to talk about. This time, however, the talk had turned to protecting a company’s intellectual property (IP). Jim had brought up the topic in the context of the looming legal … Read More
One of the privilages of blogging for SemiWiki is invitations to the top conferences around the world including the International Solid-State Circuits Conference (ISSCC) in San Francisco this week. Amazing, this conference is older than I am:
ISSCC 2013 is the 60th Conference in an incredibly long-lasting series. Following… Read More
For those of you who don’t know, Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification… Read More
(with apologies to George Harrison) Two recent Blogs over at ReRAM-Forum.com have focused on the latest in the IP field, particularly as it affects resistive memory. A high level overview of who is patenting what suggests a healthy amount of R&D is going on in the field. But looking a little deeper suggests there is much overlap… Read More
This article tries to bring out the advantages of having a functional check list. The objective is to make verification as robust as possible. Functional check list ensures the complete coverage of hardware block that is designed. This may to an extent help software developers. Creation of test plan with functional check list … Read More
You are going to be developing software for an SoC that contains an ARM Cortex-A57 64-bit CPU. Or perhaps it is an SoC containing ARM’s hybrid big.LITTLE multi-core architecture that combines one or more low power cores with some high power, high performance cores to get the best of both worlds: high throughput when it is needed… Read More
CEVA is happy to welcome new competitor in the DSP IP solution for Computer Vision and Imaging elitist club! In fact, we all know that the competition is not only good for IP customers, but is also a good way to boost innovation and propose continuously improved solutions, and Computer Vision and Imaging is one field of high creativity,… Read More
I read two blogs this week that got me to thinking about contingencies in SoC implementation. By contingency I mean using an EDA tool flow from the leading vendor for logic synthesis and then discovering that you cannot route the design without expanding the die size after a few weeks of concerted effort, then having to come up with… Read More
EDA tools come in all sizes and price ranges, so I was pleased to readthat Tanner EDAhas completed an integration with Incentia. A few months ago Tanner announced their integration with Aldec for digital simulation, and today’s announcement extends their tool suite to include digital synthesis and static timing. Here’s… Read More
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Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot