The Yield Partnership: Intel and PDF Solutions Tackle Advanced NodesOne of the most difficult things to do…Read More
Webinar: Faster Design Spec to Implementation using IP-XACTAs SoC design flows grow increasingly complex, IP-XACT…Read More
Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too LateI recently posted an overview of an upcoming…Read More
Feed Forward Intelligence: Enabling Testability in the Chiplets EraThe semiconductor industry is entering a new era…Read More
Synopsys Unifies Electrical, Thermal, Mechanical, and Optical Analysis with Multiphysics Fusion Solutions Market Leaders Including Cisco,…Read More
I have been at SNUG for the last couple of days. The big announcement is IC Compiler II. It was a big part of Aart’s keynote and Monday lunch featured all the lead customers talking about their experience with the tool.
The big motivation for IC Compiler II was to create a fully multi-threaded physical design tool that will scale… Read More
Digital verification engineers on SoC designs have adopted many techniques to help ensure first silicon success: using compiled simulators, constrained random test, simulation farms, SystemVerilog methodology, and self-checking testbenches. AMS verification has tended to be ad-hoc or sharply divided into separate analog… Read More
Light has become integral part of most of the electronic devices we use today in any sphere of influence; personal, entertainment, consumer, automotive, medical, security, and industrial and so on. It’s obvious; along with IoT (Internet-of-Things) devices, the devices to illuminate and display things will play a major role… Read More
We’re all quite twitterpated with the smartphone. Admittedly, it has taken much of the world by storm, and dominates EDA discussion because of the complex SoCs inside. Feature phones have repeatedly been declared dead, or at least disinteresting, but the numbers tell a different story.
While Europe and the US enjoy much higher… Read More
EDA start-up companies often have the advantage over established vendors by being able to start from scratch, instead of having to maintain some legacy code that no longer is competitive. But what happens when the established vendor decides to rewrite their IC implementation tools from scratch? In this case it’s good news,… Read More
The annual Design Automation Conference (DAC) is a big deal and should be of interest to students considering a career in developing software to help automate some of the toughest design and verification challenges in SoC design. Maybe the cost of attending and traveling to DAC is an issue for you. The organizers of DAC are continuing… Read More
For most of my career, I worked as a CAD and design flow engineer. In the fall of 2012, I moved to a different role, as an applications and support manager at ClioSoft Inc. In my opinion, this was a very good opportunity for me to work with other CAD engineers and teams.
Having worked with different CAD teams in my career, I have often felt… Read More
As an example of the need for real-world reliability metrics, consider a modern automobile. We can already buy a car with parking assistance, collision avoidance, autonomous braking and adaptive cruise control features. These new features depend on video image processing that requires high-performance SoC components where… Read More
Here are the top 10 reasons to use the Xilinx Vivado Design Suite to design your All Programmable Devices:
Reason number 10: Accelerate verification by over 100XThe Vivado Design Suite System Edition lets you do design at the C, C++ or systemC level. But a side-benefit is that you can use these languages for verification at performances… Read More
Mentor Graphics acquired Berkeley Design Automation this morning. The details of the deal were unannounced. This is a strong move by Mentor to challenge Cadence and Synopsys in the nanometer analog/mixed-signal market and nanometer memory characterization market, respectively. Mentor not only acquires the technology and… Read More
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs