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IC Design with No Clocks Used in a SMART Card

IC Design with No Clocks Used in a SMART Card
by Daniel Payne on 05-17-2013 at 5:21 pm

My IC design career started at Intel with DRAM chips, so I’m very familiar with clockless design because we used self-timed techniques to get maximum performance. I remember blogging about an asynchronous design company called Tiempo back in 2010, while blogging at Chip Design Magazine. A few weeks ago there was a press … Read More


Are you going to the plug fest?

Are you going to the plug fest?
by Eric Esteve on 05-17-2013 at 10:16 am

PCI Express 3.0 specification is 1000 pages long. Most of us, and most of the designers integrating PCIe gen-3 into their latest ASIC, FPGA or system will probably never read it completely, or even open it. In fact, they don’t need to read it completely, but they should care about one point, whether they buy an ASSP or a PCIe design IP:… Read More


Atrenta CEO on RTL Signoff

Atrenta CEO on RTL Signoff
by Daniel Nenni on 05-16-2013 at 9:00 pm

Most EDA companies sell tools into the main chip design and implementation flow such as simulation, synthesis, place & route, custom design and mask data prep. Atrenta is different. Nothing the company sells is in this main design flow. Instead, Atrenta focuses on pre-synthesis design analysis and optimization. Everything… Read More


AMD Reduces Power by 20%

AMD Reduces Power by 20%
by Paul McLellan on 05-16-2013 at 4:12 pm

Steve Kommrusch of AMD wrote a white paper with Calypto on how AMD reduced power by 20% on the Jaguar SoC using Calypto’s PowerPro. Dan Nenni blogged about it on SemiWiki back in February here. And now, drumroll, Steve will present the story live and in person at DAC, on Monday June 3rd at 3pm and on Wednesday June 5th at 11am. This… Read More


Cadence Technical Sessions @ #50DAC (Free Food!)

Cadence Technical Sessions @ #50DAC (Free Food!)
by Daniel Nenni on 05-16-2013 at 10:00 am


Cadence is a DAC anchor, everyone will visit their booth, so lets look at their technical sessions and put our agendas together. Lets start with the breakfast/lunch sessions because Cadence usually puts out quite a spread, we all gotta eat and free food tastes even better:

Has “Timing Signoff Innovation” Become an Oxymoron? WhatRead More


Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification

Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
by Eric Esteve on 05-16-2013 at 1:26 am

We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first … Read More


One-Stop Shop for Complete MIPI IP Solution

One-Stop Shop for Complete MIPI IP Solution
by Pawan Fangaria on 05-15-2013 at 8:00 pm

As we know mobile industry is one of the fastest growing in the electronics arena, and it has led to the emergence of several standards of interfaces between processors, devices, storage, camera, keyboard and so on. The interfaces can involve hardware as well as software and can be complex. The standards are still evolving, often… Read More


Carbon CEO on Advanceed ARM based SoC Design!

Carbon CEO on Advanceed ARM based SoC Design!
by Daniel Nenni on 05-15-2013 at 10:00 am

Carbon Design drives a lot of traffic to SemiWiki. Actually, it’s ARM driving traffic to the Carbon landing page since Carbon and ARM work closely together. When we blog about designing with ARM IP droves of people click over. Seriously, DROVES of people. Rick Lucier has deep EDA experience and has led Carbon as CEO for the … Read More


Methodics CEO on Managing Design Quality!

Methodics CEO on Managing Design Quality!
by Daniel Nenni on 05-14-2013 at 8:05 pm

Methodics is new to SemiWiki and I have to tell you I’m really enjoying working with them. Their office is in a great location and the inovation spirit runs strong. Simon Butler is an interesting guy. He first started in EDA with HLD (acquired by Cadence) and was a founder at Sabio Labs (acquired by Magma). In between those startups… Read More


Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs

Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs
by Daniel Payne on 05-14-2013 at 6:27 pm

I love it when my Acura goes months and months without any major repair issue or computer-related glitches. Cars or networks only become reliable when they are designed and built for reliability. Freescale designs SoCs for advanced automotive and networking applications, and their engineers know much about the topics of power,… Read More