Streamlining Functional Verification for Multi-Die and Chiplet DesignsAs multi-die and chiplet-based system designs become more…Read More
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The power integrity (PI) of a system is an extremely important aspect to be looked at all levels – chip, package and PCB for overall reliability of the system. At the PCB level, a DC analysis, usually based on IR drop, must ensure that adequate DC voltage, satisfying all constraints of current density and temperature, is delivered… Read More
The calls from Wall Street keep coming with basically the same set of questions: “Does Intel really have a 2-3 year process lead? Can Intel lead the foundry segment? Can Intel Lead the Mobile SoC Segment?” The feeling amongst the buy and sell side investment people is that unless Intel can lead a market they will not stay in it… Read More
Can I ask you a personal question dear reader? It is only fair, you know so much about me and all, so here goes… Why are you still hand coding you’re FPGA design? Surely you are not hand coding interfaces, like PCie, SRIO, DDR, GbE, JESD204B, HMC etc… Correct? OK, why then are you still hand coding the guts of the world’s best, super-duper… Read More
So you want to do a low power design. Join the club. Who doesn’t? Today all designs are low power, it is the biggest constraint on what we can do on a chip. Power down; power domains, variable clock rates, mixed Vt libraries. Every trick is needed. And that is not even enough. We get to put our phones on charge each evening and there… Read More
DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL designby attending… Read More
Samsung has plenty to talk about this year at DAC. The FD-SOI partnership with STMicroelectronics for example. Also the Samsung GLOBALFOUNDRIES 14nm partnership. Thus the “Paradigm Shift in the Foundry Supply Chain” theme. Samsung is also leading the pack with giveaways!
I just returned from the “Semiconductor Executive Briefing: Strategies for Next Generation Semiconductor IP Management” panel,held at the Computer History Museum, sponsored by Dassault Systèmes.
(Left to right) Moderator: Warren Savage, President and CEO, IPextreme, with panelists John Tam, Director of Business Development,… Read More
eSilicon is a fabless chip company that is credited with starting the fabless ASIC movement. You can read more about them in the ASIC chapter of SemiWiki’s new book on the fabless semiconductor industry. But why would a fabless ASIC company come to DAC?
At one level, eSilicon starts where EDA technology ends – taking a taped out chip… Read More
In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization… Read More
Imagine life without science and great minds that made life worth living! It is personalities like Newton, Thomas Alva Edison, Graham Bell, Alexander, Michael Faraday who have made us realized the true potential of science.
Imagine what would have happened if Newton had not discovered gravity? It is due to gravity that earth revolves… Read More
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