DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL designby attending our sessions at DAC. These in-depth presentations and demos by our engineers will demonstrate solutions for designers to create high quality and low power electronic systems for today’s most innovative electronic products.
Please see the topics and registration times below:
Ciena: Cutting Design and Verification Time for a Coherent Optical Processor with HLS (User Presentation)Boris Hristov from Ciena describes Ciena’s DSP design flow using Catapult[SUP]®[/SUP], and how HLS can make major reductions in ASIC development time.
Monday: 4:00 PMor Tuesday: 11:00 AM
Google: G2 VP9 Hardware Decoder Development Using Catapult HLS (User Presentation)
This session will cover Google’s successful implementation of Catapult high-level synthesis in the development of G2 VP9.
Monday: 2:00 PM
Reaching for Maximum Power Reduction at RTL using PowerPro[SUP]®[/SUP] & SLEC[SUP]®[/SUP]
We show how PowerPro’s RTL power analysis and patented optimization helps you create low power RTL and verify it with the sequential formal technology of SLEC Pro.
Monday: 11:00 AMor 5:00 PM; Tuesday: 12:00 PMor 4:00 PM; Wednesday: 10:00 AMor 2:00 PM
Why and How to Adopt a HLS and Verification Methodology
This session describes how you can reduce your RTL verification effort by 50%, and the steps needed to make it happen.
Monday: 1:00 PM; Tuesday: 10:00 AM; Wednesday: 3:00 PM
Cutting Through the Noise: A Practical Comparison between C++ and SystemC for HLS (Tutorial)
Have you ever wondered which language is the best choice for your project? This unbiased tutorial will give you the scoop.
Monday: 12:00 PMor Wednesday: 1:00 PM
Leveraging HLS to Achieve Low Power Designs: Catapult LP
Theonly HLS product to focus on power at the architecture level where the biggestimpact can be made. CatapultLP embeds Calypto’s unique PowerProtechnology “under the hood” for maximum power savings.
Tuesday: 2:00 PMor Wednesday: 11:00 AM
Calypto® Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s Catapult High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerPro product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.
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