Webinar PQC SemiwikiV4
WP_Term Object
    [term_id] => 71
    [name] => Xilinx
    [slug] => xilinx
    [term_group] => 0
    [term_taxonomy_id] => 71
    [taxonomy] => category
    [description] => 
    [parent] => 106
    [count] => 114
    [filter] => raw
    [cat_ID] => 71
    [category_count] => 114
    [category_description] => 
    [cat_name] => Xilinx
    [category_nicename] => xilinx
    [category_parent] => 106

Secret to Beating Your FPGA Competitor’s Design

Secret to Beating Your FPGA Competitor’s Design
by Luke Miller on 05-17-2014 at 6:00 am

Can I ask you a personal question dear reader? It is only fair, you know so much about me and all, so here goes… Why are you still hand coding you’re FPGA design? Surely you are not hand coding interfaces, like PCie, SRIO, DDR, GbE, JESD204B, HMC etc… Correct? OK, why then are you still hand coding the guts of the world’s best, super-duper shiny Xilinx FPGA? And yes, I did say world’s best, best in DSP, IO, SoC, IP, etc… So how do you plan on using the 8 TMACS available to you in the Xilinx Kintex-115 via the 5520 DSP? Which are the widest and fastest in the FPGA world. Can you say nice Dynamic Range?

We get comfortable don’t we? We engineers do not like risk and giving up control. I have said this before but I have not written a DSP function by hand since 2011. Been writing them in C/C++. Let’s face it the Xilinx Virtex-II Pro had like 232 DSP, and we were wowed, ‘this is it, it does not get better than this’!

I think we all agree that a VME rack of 8 boards with 3 Virtex-II Pro FPGAs per board all collapse down into a few UltraScale FPGAs. That is mind boggling, but who is doing the firmware design? Herein lies the problem. As the FPGA Blob keeps eating functionality around it, we are left with a very formidable problem of getting that system designed and integrated on that FPGA. Since I am a RADAR/EW fella, the problem at hand is usually intense very parallel math pipes. FIR filters, FFT’s, DFTs, Complex Mults, QR Decomposition, CFAR, blah, blah…Is VHDL or Verilog coding going to get you to the finish line, on time, under budget? Not to burst your bubble but probably not, and defiantly not if your competitor is using Xilinx’s Vivado HLS. (High Level Synthesis). Vivado HLS handles fixed or floating point data types. So you need weights for that Adaptive Beamformer? You can easily design a QR decomposition core in a few hours, for real, and complex data as well. From a RADAR perspective this means you can design the whole beamformer, pulse compressor and doppler filter in one Xilinx UltraScale FPGA, fixed and/or float. Same idea applies to any function you can dream of.

The above results are real examples who have tasted and seen that the power of Xilinx’s Vivado HLS is key to having the edge over the competitor. The design time is greatly reduced due to simulation of the design takes place as a compiled C/C++ executable not RTL. The Math, Latency, device usage and clock frequency are verified within minutes of the design. RTL simulation for a Doppler Filter card in a RADAR system would take days of RTL simulation and then weeks to chase down bugs to fix the design. Not so using C/C++, the simulation time is in seconds. The HLS design also accepts change and is truly portable. The same code you use in the programmable logic in the Xilinx FPGA easily compiles on the ARM core in the Zynq. Times are changing much like the days of assembly migrating to compilers. Now is the time to make the move to the most valuable tool in the Xilinx FPGA designer’s tool box, Vivado HLS.

lang: en_US

Share this post via:


There are no comments yet.

You must register or log in to view/post comments.