Bjorn Kolbeck received a PhD in Computer Science from Humboldt University in Berlin. Bjorn had previously worked at HPC centers and at Google. His experience with hyperscale architectures led him to co-found Quobyte in 2013.
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Quobyte is scale-out storage, and was designed for massive scalability and… Read More
In this episode of the Semiconductor Insiders video series, Dan is joined by Dr Greg Law, CEO of Undo, He is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg explains the history of Undo, initially as a provider of software development and debugging tools for software vendors. He explains that… Read More
Dan is joined by David Tibbetts, Chief Safety Officer at Highwire. David is a Certified Safety Professional with 20+ years of occupational safety experience in both general industry and construction settings. He is currently supporting Highwire’s hiring partners utilizing the Highwire suite of software solutions … Read More
The trend is clear, AI and HPC is moving to chiplet-based, or heterogenous design to achieve the highest levels of performance, while traditional monolithic system-on-chip (SoC) designs struggle to scale. What is also clear is the road to this new design style is not a smooth one. There are many challenges to overcome. Some are … Read More
Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions… Read More
WSTS reported 1st quarter 2025 semiconductor market revenues of $167.7 billion, up 18.8% from a year earlier and down 2.8% from the prior quarter. The first quarter of 2025 was weak for most major semiconductor companies. Ten of the sixteen companies in the table below had declines in revenue versus 4Q 2024, ranging from -0.1% from… Read More
Design-Technology Co-Optimization (DTCO) has been a foundational concept in semiconductor engineering for years. So, when Synopsys referenced DTCO in their April 2025 press release about enabling Angstrom-scale chip designs on Intel’s 18A and 18A-P process technologies, it may have sounded familiar—almost expected. … Read More
Intermediate representations (IRs) between high level languages (C++, AI, etc.) and machine language are both commonplace (witness LLVM) and a continuing active area of research. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More
PCIe is familiar to legions of PC users as a high-performance enabler for expansion slots, especially GPU-based graphics cards and M.2 SSDs. It connects higher-bandwidth networking adapters and niche applications like system expansion chassis in server environments. Each PCIe specification generation has provided a leap… Read More
As the computing industry seeks more flexible, scalable, and open hardware architectures, RISC-V has emerged as a compelling alternative to proprietary instruction set architectures. At the forefront of this revolution stands Andes Technology, offering a comprehensive lineup of RISC-V processor solutions that go far beyond… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot