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CEO Interview with Bjorn Kolbeck of Quobyte

CEO Interview with Bjorn Kolbeck of Quobyte
by Daniel Nenni on 06-01-2025 at 10:00 am

Bjoern

Bjorn Kolbeck received a PhD in Computer Science from Humboldt University in Berlin. Bjorn had previously worked at HPC centers and at Google. His experience with hyperscale architectures led him to co-found Quobyte in 2013.

Tell us about your company?

Quobyte is scale-out storage, and was designed for massive scalability and… Read More


Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law

Video EP7: The impact of Undo’s Time Travel Debugging with Greg Law
by Daniel Nenni on 05-30-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by Dr Greg Law, CEO of Undo, He is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg explains the history of Undo, initially as a provider of software development and debugging tools for software vendors. He explains that… Read More


Podcast EP289: An Overview of How Highwire Helps to Deliver Advanced Fabs with Less Cost, Time and Risk with David Tibbetts

Podcast EP289: An Overview of How Highwire Helps to Deliver Advanced Fabs with Less Cost, Time and Risk with David Tibbetts
by Daniel Nenni on 05-30-2025 at 6:00 am

Dan is joined by David Tibbetts, Chief Safety Officer at Highwire. David is a Certified Safety Professional with 20+ years of occupational safety experience in both general industry and construction settings. He is currently supporting Highwire’s hiring partners utilizing the Highwire suite of software solutions … Read More


Synopsys Addresses the Test Barrier for Heterogeneous Integration

Synopsys Addresses the Test Barrier for Heterogeneous Integration
by Mike Gianfagna on 05-29-2025 at 10:00 am

Synopsys Addresses the Test Barrier for Heterogeneous Integration

The trend is clear, AI and HPC is moving to chiplet-based, or heterogenous design to achieve the highest levels of performance, while traditional monolithic system-on-chip (SoC) designs struggle to scale. What is also clear is the road to this new design style is not a smooth one. There are many challenges to overcome. Some are … Read More


Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000
by Bernard Murphy on 05-29-2025 at 6:00 am

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions… Read More


Semiconductor Market Uncertainty

Semiconductor Market Uncertainty
by Bill Jewell on 05-28-2025 at 2:00 pm

2025 Semiconductor Market Forecast

WSTS reported 1st quarter 2025 semiconductor market revenues of $167.7 billion, up 18.8% from a year earlier and down 2.8% from the prior quarter. The first quarter of 2025 was weak for most major semiconductor companies. Ten of the sixteen companies in the table below had declines in revenue versus 4Q 2024, ranging from -0.1% from… Read More


Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies

Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies
by Kalar Rajendiran on 05-28-2025 at 10:00 am

Sassine Holding an 18A Test chip

Design-Technology Co-Optimization (DTCO) has been a foundational concept in semiconductor engineering for years. So, when Synopsys referenced DTCO in their April 2025 press release about enabling Angstrom-scale chip designs on Intel’s 18A and 18A-P process technologies, it may have sounded familiar—almost expected. … Read More


Optimizing an IR for Hardware Design. Innovation in Verification

Optimizing an IR for Hardware Design. Innovation in Verification
by Bernard Murphy on 05-28-2025 at 6:00 am

Innovation New

Intermediate representations (IRs) between high level languages (C++, AI, etc.) and machine language are both commonplace (witness LLVM) and a continuing active area of research. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More


WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition

WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition
by Don Dingee on 05-27-2025 at 10:00 am

PCIe application interface options are the primary motivation for the PCIe 7.0 transition

PCIe is familiar to legions of PC users as a high-performance enabler for expansion slots, especially GPU-based graphics cards and M.2 SSDs. It connects higher-bandwidth networking adapters and niche applications like system expansion chassis in server environments. Each PCIe specification generation has provided a leap… Read More


Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond

Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond
by Kalar Rajendiran on 05-27-2025 at 6:00 am

Overview of Andes Product Categories

As the computing industry seeks more flexible, scalable, and open hardware architectures, RISC-V has emerged as a compelling alternative to proprietary instruction set architectures. At the forefront of this revolution stands Andes Technology, offering a comprehensive lineup of RISC-V processor solutions that go far beyond… Read More