WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent DevicesEdge AI is rapidly transforming how intelligent solutions…Read More
WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPsIn today's data-driven systems—from cloud storage and AI…Read More
ChipAgents Tackles Debug. This is ImportantInnovation is never ending in verification, for performance,…Read More
Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and AnalysisIn a major announcement at the 2025 Design…Read More
CEO Interview with Faraj Aalaei of CognichipFaraj Aalaei is a successful visionary entrepreneur with…Read More
My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More
Everyone is somewhat focused on the march of process nodes. Moore’s Law, although I think that with the breach between technology and cost that may be changing. Moore’s Law was about the lowest cost way to get a given number of transistors manufactured. But now the lowest cost and the highest density are diverging. … Read More
Five years ago TSMC started 28nm mass production and it went on to become one of the most versatile and successful process technologies in history. The first wave was triggered by an unprecedented demand for application processors from smartphone and tablet vendors. Today it’s widely assumed that 28nm demand will continue growing… Read More
Managing any design data management system requires a policy on how often users should be submitting their changes to the central repository. If users commit frequently with less local testing then other users will more likely see errors. If commits are done less often, but with better testing, then other users are protected from… Read More
Today, an SoC can have multiple instances of an IP and also instances of many different IPs from different vendors. Every instance of an IP can work in a separate mode and requires a dedicated power arrangement which may only be formalized at the implementation stage. The power intent, if specified earlier, will need to be re-generated… Read More
Samsung’s Exynos 7420 system-on-chip (SoC) is now at the top of the world when it comes to performance and power efficiency benchmarks. It’s also won accolades as the first mobile chipset manufactured using the 14nm FinFET fabrication process.
However, the mobile chipsets landscape is hypercompetitive, and there… Read More
Actual users of circuit simulators told their design and simulation stories at DAC during a luncheon sponsored by Synopsys on June 8th. I always prefer to hear from a design engineer versus a marketing person about what tool they use for circuit simulation, and how it helps them analyze their design goals. This year there were engineers… Read More
I talked recently about the Intel acquisition of Altera which seems to be all about using FPGA technology to build custom accelerators for the datacenter. Some algorithms, especially in search, vision, video and so on map much better onto a hardware fabric than being implemented in code on a regular microprocessor.
So if the heart… Read More
Synopsys is launching a broad IP portfolio to support SoC development dedicated to emerging automotive complexes functions, like Driver Assistance (ADAS), Driver Information, Vehicle Network or Infotainment. I was never involved into IC design for Automotive, but I have designed ASIC for avionics (CFM56 motor control) or… Read More
I expect most of you have already heard the sad news through other channels: Gary Smith died last Friday, July 3rd, from pneumonia in Flagstaff, Arizona.
I must have first met Gary back in Dataquest days when I was at VLSI Technology. Gartner then acquired Dataquest and eventually shut down the EDA practice and laid Gary off. He then… Read More
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Facing the Quantum Nature of EUV Lithography