The recent mega acquisition of Broadcom Corp by Avago can be traced all the way back to Silicon Valley stalwart Hewlett Packard (founded in a two car Palo Alto garage in 1939). Even more interesting is the man behind the acquisition and how he got to where he is today.Avago began as the semiconductor products division of HP in 1961, … Read More



Coventor prepping MEMS for CMOS integration
About 11 months ago, I wrote a piece titled “Money for data and your MEMS for free.” In that, I took on the thinking that TSMC is just going to ride into town, fab trillions of IoT sensors, and they all will be 2.6 cents ten years from now. Good headline, but the technology and economics are not that simple. This may be the semiconductor … Read More
12 Reasons to Attend this Annual User Group Meeting for Transistor-level IC Designers
My first job out of college was transistor-level circuit design of DRAMs at Intel, so I’ve continued to be fascinated with both the craft and science of designing, optimizing, verifying and debugging custom ICs. Last October I traveled to Munich, Germany to attend a two day user group meeting for engineers using tools from… Read More
A FinFET BSIM-CMG model update from UC-Berkeley
Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php… Read More
Secured SAM A5D4 MCU for Industrial, Fitness or IoT Display
The new SAMA5D4, ARM Cortex-A5-based, expands the SAMA5 microprocessors family, adding a 720p resolution hardware video decoder to target Human Machine Interface (HMI), control panel and IoT applications when high performance display capability are required. Cortex-A5 offers raw performance of 945 DMIPS (@ 600 MHz) completed… Read More
Nine Cost Considerations to Keep IP Relevant –Part2
In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More
Moore’s law limitations and gravitational collapse at lower process nodes
As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for… Read More
Solidly Across the Chasm
Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?
See also Getting EDA Across the Chasm: 15 Rules Before and 5 After
The founding team of Solido:
- discovered process variation for analog was a problem as companies
What NoCs with virtual channels really do for SoCs
Most of us understand the basic concept of a virtual channel: mapping multiple channels of traffic, possibly of mixed priority, to a single physical link. Where priority varies, quality of service (QoS) settings can help ensure higher priority traffic flows unimpeded. SoC designers can capture the benefits of virtual channels… Read More
Something Old, Something New…EDA and Verification
When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should … Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot