There’s a lot of discussion these days on IoT applications, architectures, communication, security and more, all very good stuff, but little debate on how these devices will be powered. If you can plug them in, this maybe isn’t an issue (though we may need to think about increased demand on our overstrained power generation infrastructure).… Read More
DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime MonitoringAs AI models grow exponentially, the infrastructure supporting…Read More
Sophisticated soundscapes usher in cache-coherent multicore DSPDigital audio processing is evolving into an art…Read More
A Quick Look at Agentic/Generative AI in Software EngineeringAgentic methods are hot right now since single…Read More
Improve Precision of Parasitic Extraction for Digital DesignsBy Mark Tawfik Parasitic extraction is essential in…Read More
IEDM 2015 Blogs – Part 1 – Overview
The International Electron Devices Meeting (IEDM) is one of, if not the premier conference for semiconductor process technology. The 2015 meeting just finished up on Wednesday, December 9th.
This year’s meeting was held from Saturday, December 5[SUP]th[/SUP] through Wednesday, December 9[SUP]th[/SUP] in Washington DC.… Read More
3 flavors of TMR for FPGA protection
Back in the microprocessor stone age, government procurement agencies fell in love with the idea of radiation hardened parts that might survive catastrophic events. In those days, before rad-hard versions of PowerPC and SPARC arrived, there were few choices for processors in defense and space programs.
One of the first rad-hard… Read More
The Mobility Imperative and the Untethered Consumer
Consumers want to be able to go where they want, when they want. They want televisions to be seamlessly synchronized with tablets, phones, laptops, and automobiles. They want all their communication, information, and entertainment to be available immediately, with high resolution, all the time. Recently the automobile industry… Read More
Does Managing Tools as if they are IP Make Sense?
Years ago I thought that chip design companies would embrace the latest technology and be eager to adopt new tools. What I learned was that the people implementing and managing design projects were taking a lot of risks with almost every aspect of their projects. What they most wanted is to minimize risk from the design process – especially… Read More
5 Verification Challenges of IoT Solved by Emulation
Software-centric Emulation environment takes the forefront in modern SoC verification. As more and more devices are IoT enabled, the SoCs have to make special provisions to factor many things including communication, power usage, and network switching, and so on. Also, the demand for an SoC (specifically for smartphone which… Read More
Cadence Enters the RTL Power Estimation Game
At the Cadence front-end summit last week, Jay Roy presented the Cadence Joules solution for RTL (and gate-level) power estimation. Jay is ex-Apache, so knows his way around RTL power estimation which should make Joules a product to watch. Joules connects very natively to Palladium for power characterization for realistic software… Read More
New Book: Mobile Unleashed!
This is the origin story of technology super heroes: the creators and founders of ARM, the company that is responsible for the processors found inside 95% of the world’s mobile devices today. This is also the evolution story of how three companies – Apple, Samsung, and Qualcomm – put ARM technology in the hands of billions of people… Read More
The Twists and Turns of Xilinx vs Altera!
The battle between Xilinx and Altera continues to be one of the more interesting stories to cover. It really is the semiconductor version of a reality TV show. In the beginning it was two fabless companies partnered with rival foundries going head-to-head controlling a single market that touches a variety of industries.
Then things… Read More
Syncing Up CDC Signals in Low Power Designs
So far in my blog series on low power we’ve looked broadly at what’s changing in the low power verification landscape and focused on a new methodology developed by Mentor Graphics and ARM called successive refinement, which is now included in the UPF standard. Power management techniques create their own brand of clock domain crossing… Read More
Memory Innovation at the Edge: Power Efficiency Meets Green Manufacturing