Most of my investments are associated with large changes in the semiconductor industry. These changes create opportunities for new and disruptive technologies. I also look to find solutions that provide a compelling reason to adopt a new technology or approach. When talking about a new approach, it often takes longer to overcome… Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read MoreIP-XACT The Answer for IP Reuse
To a lawyer, the term intellectual property means just about anything intangible that has value. However, when you bring that term up in the context of semiconductor design, it means something pretty specific to most people. Yet the implied meaning of the term intellectual property (IP) within the semiconductor field has changed… Read More
Cloud-based Functional Verification
The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More
The Answer to Why Intel PMOS and NMOS Fins are Different Sizes
Like many others, we have often wondered why the PMOS fins on advanced microprocessors from Intel are narrower than the NMOS fins (6nm versus 8nm). This unusual dimensional difference first occurred at the 14nm node and it coincided with the introduction of Solid State Doping (SSD) of the fins at this node.
We have concluded that… Read More
Which Way is Up for Lyft, Uber?
Lyft’s initial public offering was expected to be the biggest tech offering in two years. A public offering is very much like an elevator and everyone getting on the elevator wants to go up. It’s worth noting as the doors open on the Lyft IPO elevator, General Motors is likely to be getting off – and they are not alone.… Read More
The ESD Alliance Welcomes You to an Evening with Jim Hogan and Paul Cunningham
An informal “Fireside Chat” like no other featuring Jim Hogan, managing partner of Vista Ventures, LLC., and Paul Cunningham, Cadence’s corporate vice president and general manager of the system verification group, is in the works for Wednesday, April 10.
Hosted by the ESD Alliance, a SEMI Strategic Association Partner, at … Read More
Google Stadia is Here. What’s Your Move, Nvidia?
On March 16, 2019, Google introduced the world to its cloud-based, multi-platform gaming service, Stadia. Described as “a gaming platform for everyone” by Google CEO Sundar Pichai at the Game Developers Conference, Stadia would make high-end games accessible to everyone. The video gaming industry, as we know it, will never … Read More
So What is Quantum Computing Good For?
If you have checked out any of my previous blogs on quantum computing (QC), you may think I am not a fan. That isn’t entirely correct. I’m not a fan of hyperbolic extrapolations of the potential, but there are some applications which are entirely sensible and, I think, promising. Unsurprisingly, these largely revolve around applying… Read More
My Thoughts on Cadence in the Cloud
The cloud is a highly popular term that a lot of people don’t fully understand. If you are one of those people please read on as I will share my experience, observations, and opinions. Even if you are a cloud aficionado you may want to catch up on what’s new with EDA cloud services so again read on.
When we first started SemiWiki 9 years … Read More
Solving the EM Solver Problem
The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More


An Insight into Building Quantum Computers