Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency… Read More
2026 Outlook with Richard Hegberg of Caspia TechnologiesTell us a little bit about yourself and…Read More
Siemens EDA Illuminates the Complexity of PCB DesignAs heterogeneous multi-die design becomes more prevalent, the…Read More
Accelerating Advanced FPGA-Based SoC Prototyping With S2CHaving spent a significant amount of my career…Read More
Verification Futures with Bronco AI Agents for DV DebugVerification has become the dominant bottleneck in modern…Read MoreOnline Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)
Our friends at Threshold Systems have a new ONLINE class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last February. This is normally a classroom affair but to accommodate the recent COVID-19 travel restrictions it is being offered virtually.
As part of the previous class we did… Read More
SiFive in a Virtual World Webinar Series 2020
Introducing the SiFive Connect Webinar Series –A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions
After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached… Read More
Wally Rhines: Mentoring Generations of Semiconductor and EDA Professionals
I had the good fortune to catch a live webinar recently that was quite compelling – Conversation with Dr. Walden Rhines: Predicting Semiconductor Business Trends After Moore’s Law! Dr. Rhines, known to most as Wally, doesn’t need much of an introduction. Any semiconductor or EDA professional knows who he is and what he’s accomplished.… Read More
Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki … Read More
Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020
Because of significant $4 billion in equipment pull-ins in Q4 from sales in Asia, I was reducing my semiconductor wafer front-end (WFE) equipment revenue growth from an earlier +5% to 0% in 2020. Now, based on CORVID-19, I am further reducing revenue growth to -6.9%.
Chart 1 also shows the cyclical nature of semiconductors and semiconductor… Read More
Learning to Live with the Gaps Between Design and Verification
Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the… Read More
A cautionary tale for the digital economy
COVID-19 underscores the importance of US-based production for strategic industries
The COVID-19 pandemic has drawn intense focus on the need to repatriate pharmaceutical manufacturing back to the United States. The increased awareness that a strategic adversary manufactures or controls up to 80% of the active pharmaceutical… Read More
Best Practices for IP Reuse
As someone who was heavily involved with rules for IP reuse for many years, I have a major sense of déja vu in writing again on the topic. But we (in SpyGlass) were primarily invested in atomic-level checks in RTL and gate-level designs. There’s a higher level of best practices in process we didn’t attempt to cover. ClioSoft just released… Read More
Lithography Resolution Limits: Paired Features
As any semiconductor process advances to the next generation or “node”, a sticky point is how to achieve the required higher resolution. As noted in another article [1], multipatterning (the required use of repeated patterning steps for a particular feature) has been practiced already for many years, and many have… Read More



AI Bubble?