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Intel 7NM Slip Causes Reassessment of Fab Model

Intel 7NM Slip Causes Reassessment of Fab Model
by Robert Maire on 07-23-2020 at 5:00 pm

Intel vs TSMC

Waving white surrender flag as TSMC dominates-
The quarter was a success but the patient is dying-
Packaging now critical as Moore progress stumbles-
Intel reported a great quarter but weak H2 guidance-
But 7NM slip and “fab lite” talk sends shockwaves-

Intel reported a great quarter beating numbers all around with… Read More


The Polyglot World of Hardware Design and Verification

The Polyglot World of Hardware Design and Verification
by Daniel Nenni on 07-23-2020 at 10:00 am

SemiWiki article

It has become a cliché to start a blog post with a cliché, for example “Chip designs are forever getting larger and more complex” or “Verification now consumes 60% of a project’s resources.” Therefore, I’ll open this post with another cliché: “Designers need to know only one language, but verification engineers must know many.”… Read More


Alchip Delivers Cutting Edge Design Support for Supercomputer Processor

Alchip Delivers Cutting Edge Design Support for Supercomputer Processor
by Mike Gianfagna on 07-23-2020 at 6:00 am

MN 3 Supercomputer

Alchip issued a press announcement recently entitled Alchip Provides Supercomputer Processor Design Support. The release is literally a tour de force of technology, with many advanced design and packaging accomplishments. First, let’s examine the basics of the design.

Preferred Networks, Inc (PFN) is the customer. They … Read More


Die shrink: How Intel scaled down the 8086 processor

Die shrink: How Intel scaled down the 8086 processor
by Ken Shirriff on 07-22-2020 at 2:00 pm

Intel 8086 Comparison

The revolutionary Intel 8086 microprocessor was introduced 42 years ago this month so I’ve been studying its die.1 I came across two 8086 dies with different sizes, which reveal details of how a die shrink works. The concept of a die shrink is that as technology improved, a manufacturer could shrink the silicon die, reducing… Read More


How About a Faster Fast SPICE? Much Faster!

How About a Faster Fast SPICE? Much Faster!
by Tom Simon on 07-22-2020 at 10:35 am

Analog FastSPICE eXTreme

When Analog FastSPICE was first introduced in 2006 it changed the landscape for high performance SPICE simulation. During the last 14 years it has been used widely to verify advanced nanometer designs. Of course, since then the most advanced designs have progressed significantly, making verification even more difficult. Just… Read More


Accelerating High-Performance Computing SoC Designs with Synopsys IP

Accelerating High-Performance Computing SoC Designs with Synopsys IP
by Daniel Nenni on 07-22-2020 at 6:00 am

Synopsys DesignWare IP

Semiconductor IP is one of the most talked about topics on SemiWiki. Always has been, always will be. Synopsys is also one of the most talked about topics on SemiWiki and IP is a very big part of that, absolutely.

After reading Eric Esteve’s latest IP Report I Googled around and found some interesting things. First, I found a Brief HistoryRead More


PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem

PLDA – Delivering Quality IP with a Solid Verification Process and an Extensive Ecosystem
by Mike Gianfagna on 07-21-2020 at 10:00 am

Screen Shot 2020 07 13 at 7.04.46 PM

For those who design advanced and complex SoCs, the term “off-the-shelf IP” can be elusive. While this approach works for a wide range of IP titles, the pressure for maximum performance or minimum power can lead to custom-tailoring requirements for the IP.

PLDA has seen these requirements for the class of complex, high-performance… Read More


Quantifying the Benefits of AI in Edge Computing

Quantifying the Benefits of AI in Edge Computing
by Bernard Murphy on 07-21-2020 at 6:00 am

Architectures for Edge computing

Many of us are now somewhat fluent in IoT-speak, though at times I have to wonder if I’m really up on the latest terminology. Between edge and extreme edge, fog and cloud, not to mention emerging hierarchies in radio access networks – how this all plays out is going to be an interesting game to watch. Ron Lowman, DesignWare IP Product… Read More


Cadence Defines a New Signoff Paradigm with Tempus PI

Cadence Defines a New Signoff Paradigm with Tempus PI
by Mike Gianfagna on 07-20-2020 at 10:00 am

Screen Shot 2020 06 24 at 11.24.34 PM

Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More


Perforce Software Acquires Methodics!

Perforce Software Acquires Methodics!
by Daniel Nenni on 07-20-2020 at 6:00 am

image press release perforce methodics

This has got to be one of the most interesting and disruptive EDA acquisitions I have seen in some time. Another one that comes to mind is Siemens acquiring Mentor Graphics. We have been covering EDA PLM companies since the start of SemiWiki and have worked with most of them. If I had to keep score I would say it’s about even but … Read More