Lip-Bu (Cadence CEO) sure knows how to draw a crowd. For the opening keynote in CadenceLIVE (Americas) this year, he reprised his data-centric revolution pitch, followed by a talk from a VP at AWS on bending the curve in chip development. And that was followed by a talk by a Facebook director of strategy and technology on aspects of… Read More





WEBINAR: Addressing Verification Challenges in the Development of Optimized SRAM Solutions with surecore and Mentor Solido
After spending a significant amount of my career in the IP library business it was an easy transition to Solido Design. I spent 10+ years traveling the world with CEO Amit Gupta working with the foundries and their top customers. In fact, the top 40 semiconductor companies use Solido. IP companies are also big Solido users including… Read More
Webinar: Maximize Performance Using FPGAs with PCIe Gen5 Interfaces
FPGAs are a popular method to implement hardware accelerators for applications such as AI/ML, SmartNICs and storage acceleration. PCIe Gen5 is a high bandwidth communication protocol that is a key enabler for this class of applications. Putting all this together presents significant demands on the FPGA for performance and … Read More
Creating Analog PLL IP for TSMC 5nm and 3nm
TSMC’s Open Innovation Platform’s main objective is to create and promote partnership for producing chips. This year’s OIP event included a presentation on the joint efforts of Silicon Creations, Mentor, a Siemens business and TSMC to produce essential PLL IP for 5nm and 3nm designs. The relentless push for smaller geometries… Read More
Can you really meet your SoC design schedule without a good GUI?
Talk to the members of a digital design team and you will always find two types of users. One who likes using the GUI while working on his design and the other who is passionate about using scripts and the command line options. This is akin to the two camps of users who either love either good old Vi/Vim or the ever versatile Emacs editor.… Read More
Data Management for the Future of Design
Data management is one of those core technologies which is absolutely essential in any professional design operation. You must use a data management system; you just want it to be as efficient as possible. Most of us settled on one of a few commercial or open-source options. The problem seemed more or less solved. As usual in chip … Read More
Protocol in Depth – USB
The USB protocol is a very complex protocol, so there is no way i can explain every detail in a post, but i can let much more easy to understand what happens in a bit level.
There isn’t much good material for easy understand about USB, so i made some assumptions for make easier explain everything. In this post i’ll explain… Read More
Smartphone Processor Trends and Process Differences down through 7nm
This comparison of smartphone processors from different companies and fab processes was originally going to be a post, but with the growing information content, I had to put it into an article. Here, due to information availability, Apple, Huawei, and Samsung Exynos processors will get the most coverage, but a few Qualcomm Snapdragon
Making Full Memory IP Robust During Design
Looking at a typical SoC design today it’s likely to contain a massive amount of memory IP, like: RAM, ROM, register files. Keeping memory close to the CPU makes sense for the lowest latency and highest performance metrics, but what about process variations affecting the memory operation? At the recent DAC conference held… Read More
CEO Interview: Charlie Janac of Arteris IP
Charlie Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans over 20 years and multiple industries including electronic design automation, semiconductor capital equipment,… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet