Synopsys Announces Expanding AI Capabilities and EDA AI LeadershipIn the fast-paced semiconductor industry Synopsys has redefined…Read More
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)Introduction: The Historical Roots of Hardware-Assisted Verification The…Read More
Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
The Importance of Productizing AI. Everyday ExamplesKeeping up with the furious pace of AI…Read More
We all know the signal integrity and power integrity challenges of high-performance system design. It used to be enough to design a robust chip. Now, the interaction between the chip, the substrate/package and the PCB all matter. If your design is 2.5D, as many are these days, the problems just gets worse. Chiplets are becoming… Read More
Last month, I discussed a webinar about HCL VersionVault – HCL VersionVault Delivers Version Control and More. This webinar introduced the HCL VersionVault product. This post will discuss a new video entitled “How HCL VersionVault Works – Directory Versioning.”
To recap, VersionVault delivers a lot of … Read More
It’s no secret that innovation in AI chip architectures is on a tear. When you put together the spatial complexity of highly parallelized algorithms with the need to localize memory accesses on-chip to the greatest extent possible, we’re seeing a proliferation of all kinds of domain-specific architectures. Which in the normal… Read More
This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The talk covered here focuses on a complete on-die clock … Read More
Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time. This article is the last of three that attempts to summarize the highlights of the presentations. This article focuses on the technology design enablement roadmap, as described by Cliff Hou, SVP, R&D.
Key Takeaways… Read More
There are many reasons today for dividing up large monolithic SoCs into chiplets that are connected together inside a single package. Let’s look at just some of these reasons. Many SoCs share a common processing core with application specific interfaces and specialized processing engines. Using chiplets would mean that it is… Read More
In 2016 SemiWiki published a book “Prototypical: The Emergence of FPGA-Based Prototyping for SoC Design”. Today we are writing Prototypical II since a LOT of prototyping innovation has happened in the last four years, absolutely.
For example:
Quad 10M Prodigy™ Logic System extends the capacity leadership to simplify… Read More
When we think of wireless it is natural to wonder “which one – cellular, Wi-Fi, BLE?” Our phones support everything but those are pricey devices. What if we wanted the same combo wireless option in a low-cost IoT device, maybe something that only need to send a small amount of data periodically? Logistics applications are a good example.… Read More
TSMC held their very popular Open Innovation Platform event (OIP) on August 25. The event was virtual of course and was packed with great presentations from TSMC’s vast ecosystem. One very interesting and relevant presentation was from Dolphin Design, discussing the delivery of high-performance audio processing using TSMC’s… Read More
Recently, TSMC held their 26th annual Technology Symposium, which was conducted virtually for the first time. This article is the second of three that attempts to summarize the highlights of the presentations. This article focuses on the TSMC advanced packaging technology roadmap, as described by Doug Yu, VP, R&D.
Key… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet