Understanding Intel’s future means understanding Intel’s past
Yes, there are two paths you can go by, but in the long run. There’s still time to change the road you’re on.
Intel is at a crossroad. The road they have been on since inception, and the road that has differentiated them from the rest of the pack… Read More
Clock domain crossing (CDC) analysis is unavoidable in any modern SoC design and is challenging enough to verify in its own right. CDC plus low power management adds more excitement to your verification task. I wrote on this topic for another solution provider last year. This time I want to intro an interesting twist on the problem,… Read More
The Electronic System Design (ESD) Alliance (a SEMI Technology Community) recently released their regular report on EDA revenue for Q3, 2020 . While the report is a normal occurrence, the numbers in this particular report are anything but normal. I have been reviewing these reports for many years, and I honestly can’t remember… Read More
Of the three types of materials used in microelectronics – i.e., semiconductors, metals, and dielectrics – the first two often get the most attention. Yet, there is a pressing need for a rich variety of dielectric materials in device fabrication and interconnect isolation to satisfy the performance, power, and reliability … Read More
FPGAs have played an important role in the growth of key markets, including networking, storage, mobile devices, etc. They offer a unique set of capabilities that ASICs, CPUs and GPUs find hard to match. FPGAs are wire-speed, programmable integrated circuits that accelerate data and applications. The ability to reprogram … Read More
We all know that design complexity is increasing at a fast pace. There’s always more analysis to run on larger and larger volumes of data. During tapeout, these demands can grow by an order of magnitude. Successful design projects need to add huge amounts of CPU, memory and storage for short bursts of time during tapeout to meet their… Read More
For advanced lithography used to shrink semiconductor device features according to Moore’s Law, resolution limits are an obvious consideration. It is often perceived that the resolution limit is simply derived from a well-defined equation, but nothing can be further from the truth.
Optical Lithography: the fine print
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Podcast EP2: Moore’s Law, Dead or Alive?by Daniel Nenni on 01-08-2021 at 10:00 amCategories: Uncategorized
Dan and Mike are joined by Dr. Walden Rhines for a scenic tour of Moore’s Law. The genesis and evolution of Moore’s Law are discussed, along with the fundamental processes that have driven it. How the technology world continues to grow and innovate in spite of a slowing of Moore’s Law is a central theme of the discussion.… Read More
On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More
Quantum Computing Technologies and Challenges