When Design Gets Faster, the Bottleneck Moves Through the Physical StackAI can compress the path to tape-out. The…Read More
Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung FoundryAdvanced semiconductor packaging has become essential to improving…Read More
Semicon West: Transforming Tomorrow One Chip at a TimeSEMICON West 2026 arrives at a pivotal moment…Read More
CEO Interview with Timothy Regan of IN2FABTimothy Regan has substantial experience in analog/ mixed…Read More
The $9.5 Billion Design IP Market: Shifting Boundaries, Arm's Monopoly, and the RISC-V ResponseWhile semiconductor design intellectual property (IP) is a…Read More
At the recent Design Automation Conference, Cadence presented their methodology for incorporating performance degradation measures due to device aging into a static timing analysis flow. [1] (The work was a collaborative project with Samsung Electronics.) This article reviews the highlights of their presentation.
Background… Read More
With the slowing down of Moore’s law , the industry as a whole has been working on various ways to maintain the rate of growth and advancements. A lot has been written up about various solutions being pursued to address specific aspects. The current era is being referred to by different names, SysMoore being one that Synopsys uses.… Read More
Tuesday at DAC was actually my very first time attending a technical session, and the presentation from Nebabie Kebebew, Siemens EDA, was called, Mitigating Variability Challenges of IPs for Robust Designs. There were three presentations scheduled for that particular Designer, IP and Embedded Systems track, but with the COVID… Read More
Veriest recently hosted a webinar focusing on RISC-V as a forerunner of ongoing open-source revolution in chip design. Speakers were distinguished professionals from industry and academia. Webinar covered topics from market trends to open-source hardware initiatives, tools and methodologies.
Zvonimir Bandić: RISC-V … Read More
Dan is joined by Balaji Baktha, founder and CEO of Ventana Micro. Balaji explores the application of RISC-V in high-performance applications and the specific advantages of a chiplet-based approach.
RISC-V Summit Panel: https://www.youtube.com/watch?v=duZaAhWxhWM
The views, thoughts, and opinions expressed in these… Read More
I’ve been noticing over the last few years that electronic design automation (EDA) vendors just love to talk about artificial intelligence (AI) and machine learning (ML), sometimes with deep learning (DL) and neural networks tossed in as well. It can get a bit confusing since these terms are used in two distinct contexts. The first… Read More
Combining simulation and symbolic methods is an attractive way to excite rare branches in block-level verification, but is this method really scalable? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always,… Read More
In 2014, many of the customers that my team and I supported in North America were still using HFSS 3D to model boards and packages. These customers were content with that interface, able to get their models setup quickly, and were okay with the solution times because when HFSS gave them an answer, they knew it was the right answer. I … Read More
The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.
Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More
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Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry