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2021 will be the year of DRAM!

2021 will be the year of DRAM!
by Robert Maire on 11-15-2020 at 6:00 am

Robert Maire Bloomberg

2020 has been a NAND growth year-2021 will be the year of DRAM. While foundry logic has gotten all the credit in 2020 the reality is that NAND has been up 2X in 2020 for semiconductor equipment provider Applied Materials (AMAT). It is expected that NAND will be flat in 2021 while DRAM will take over the growth slot with foundry/logic … Read More


The History and Significance of Power Optimization, According to Jim Hogan

The History and Significance of Power Optimization, According to Jim Hogan
by Mike Gianfagna on 11-13-2020 at 10:00 am

Jim Hogan

Power seems to be on everyone’s mind these days. Hyperscale data centers worry about operating costs unless power is optimized. The AI accelerators in the Edge can’t be effective without optimized power. Advanced 2.5 and 3D packages simply can’t remove the heat unless power is optimized.  And then there’s all those gadgets we … Read More


CEO Interview: Dr. Chouki Aktouf of Defacto

CEO Interview: Dr. Chouki Aktouf of Defacto
by Daniel Nenni on 11-13-2020 at 6:00 am

Defacto CEO Interview Chouki Aktouf

“For more than 18 years, we never stopped innovating at Defacto. We are aware of EDA Mantra “Innovate or Die!”. Innovation is in our DNA, and we never stopped adding new automated capabilities to the SoC design community to help facing complexity and cost challenges, which increase every year.”

Before founding Defacto… Read More


Mentor Offers Next Generation DFT with Streaming Scan Network

Mentor Offers Next Generation DFT with Streaming Scan Network
by Tom Simon on 11-12-2020 at 10:00 am

Streaming Scan Network

Design for test (DFT) requires a lot of up-front planning that can be difficult to alter if testing needs or performance differ from initial expectations. Hierarchical methodologies help in many ways including making it easier to reduce on chip resources such as the number of test signals. Also, hierarchical test allows for speed-ups… Read More


Agile and DevOps for Hardware. Keynotes at DVCon Europe

Agile and DevOps for Hardware. Keynotes at DVCon Europe
by Bernard Murphy on 11-12-2020 at 6:00 am

Agile and DevOps for Hardware

Paul Cunningham (Verification CVP/GM at Cadence) initiated our monthly Innovation in Verification blog to hunt for novel ideas in verification, breaking past the usual steady, necessary but undramatic pace of incremental advances. I attended a couple of sessions from DVCon Europe recently, and was encouraged to hear a couple… Read More


SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference

SiFive Expands RISC-V Technology and its Ecosystem at the Fall Linley Processor Conference
by Mike Gianfagna on 11-11-2020 at 10:00 am

SiFive Expands RISC V Technology and its Ecosystem at the Fall Linley Processor Conference

 

As the Linley Fall Processor Conference winds down, there are certain presenting companies that left a lasting impression.  SiFive is one of those companies. On October 21, SiFive introduced the newest member of the SiFive Intelligence family of processor coresSiFive Intelligence family of processor cores, based on… Read More


Prototyping with the Latest and Greatest Xilinx FPGAs

Prototyping with the Latest and Greatest Xilinx FPGAs
by Daniel Nenni on 11-11-2020 at 6:00 am

Prototyping with the Latest and Greatest Xilinx FPGAs

I was reading the S2C press release announcing their new FPGA prototyping platform based on the Xilinx UltraScale+ VU19P FPGA, and how the new FPGA will accelerate billion gate FPGA prototyping, and I was struck by the stunning implications of this announcement.  Not that billion gate SoC designs can now be prototyped with FPGAs,… Read More


Aldec Adds Simulation Acceleration for Microchip FPGAs

Aldec Adds Simulation Acceleration for Microchip FPGAs
by Tom Simon on 11-10-2020 at 10:00 am

Simulation Acceleration

Despite the fact that FPGA based systems make it easy to add ‘hardware in the loop’ for verification, the benefits of HDL and gate level simulation are critical for finding and eliminating issues and bugs. The problem is that software simulators can require enormous amounts of time to run full simulations over sufficient time intervals… Read More


WEBINAR: Differentiated Edge AI with OpenFive and CEVA

WEBINAR: Differentiated Edge AI with OpenFive and CEVA
by Bernard Murphy on 11-10-2020 at 6:00 am

Enablin AI Vision at the edge min

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir… Read More


Post Election Fallout-Let the Chips Fall / Rise Where They May

Post Election Fallout-Let the Chips Fall / Rise Where They May
by Robert Maire on 11-09-2020 at 10:00 am

US China Trade War
  • Changing US administration likely positive for chips & tech
  • Stepping back from the brink of a potential ugly trade war
  • Likely increased Covid/tech spend- War with Big Tech is over
  • Tech & Chips had a lot riding on the elections outcome

As compared to previous presidential elections, this one likely has much more impact on… Read More