A company that gets its products to market first stands to gain a competitive edge in the market place. This is even more so in the highly competitive and innovative semiconductor industry. At the same time, designing chips is a very challenging task that involves iterative steps that are computation, memory and storage intensive.… Read More





Cadence Tempus Update Promises to Transform Timing Signoff User Experience
Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More
Are We Done with ICE Vehicles?
U.S. President Joe Biden served notice on the automotive industry that he expects auto makers to shift 50% of vehicle sales to those with electric power trains by 2030. Of course, he included plug-in hybrids in the mix – perhaps in deference to Toyota – and Tesla was oddly absent from the announcement made on the South… Read More
Podcast EP34: IP Management for Early Stage Semiconductor Companies
Dan and Mike are joined by Michael Munsey, senior vice president of marketing, business development and corporate strategy at Perforce. Michael discusses the unique IP management requirements of early stage semiconductor companies and how to address these requirements. The risks associated with a sub-optimal approach are… Read More
Have STA and SPICE Run Out of Steam for Clock Analysis?
At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More
Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target
Designing an ASIC is little bit like trying to hit the bullseye, in the dark. I’ve spent several decades in the ASIC business I can tell you this is what it’s like from first-hand experience. When the design team sets out to build a custom chip to make their product better, faster, more robust, etc. (pick the words you like), there is … Read More
Package Pin-less PLLs Benefit Overall Chip PPA
SOCs designed on advanced FinFET nodes like 7, 5 and 3nm call for silicon-validated physical analog IP for many critical functions. Analog blocks have always been node and process specific and their development has always been a challenge for SOC teams. Fortunately, there are well established and endorsed analog IP companies… Read More
Semiconductor Growth to Continue in 2022
The semiconductor market showed powerful growth in 2Q 2021, up 8.3% from 1Q 2021 and up 29% from a year earlier, according to WSTS. Most major semiconductor companies experienced substantial revenue growth in the quarter. The memory companies were especially strong, with 2Q 2021 versus 1Q 2021 revenue (in local currency) up 19.6%… Read More
TSMC Wafer Wars! Intel versus Apple!
The big fake news last week came from a report out of China stating that TSMC won a big Intel order for 3nm wafers. We have been talking about this for some time on SemiWiki so this is nothing new. Unfortunately, the article mentioned wafer and delivery date estimates that are unconfirmed and from what I know, completely out of line. … Read More
Controlling the Automotive Network – CAN and TSN Update
Cars are hotbeds of systems innovation. I’ve been fortunate to be asked to write about many of these areas, from the MEMS underlying sensors to ISPs and radars, intelligent imaging and sensor fusion. And many aspects of design for safety within the SoCs around a car. But I haven’t written much about the networks connecting these … Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet