Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status QuoAt Hot Chips 2025, Philippe Sauter of ETH…Read More
GlobalFoundries 2025 Update GTS25"GTS25 brings together leaders from across the semiconductor…Read More
Synopsys Enables AI Advances with UALinkThe evolution of hyperscale data center infrastructure to…Read More
Revolutionizing Chip Packaging: The Impact of Intel's Embedded Multi-Die Interconnect Bridge (EMIB)In an era dominated by artificial intelligence (AI),…Read More
Lauro Rizzatti recently interviewed Andy Meier, product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy is a product manager in the Scalable Verification Solutions Division at Siemens EDA. Andy has held positions in the electronics and high-tech fields during his 20-year career including: Sr.… Read More
The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More
The success of modern battery-powered products depends as much on useful operating time between charges as on functionality. FinFET process technologies overtook earlier planar CMOS in part because they significantly reduce leakage power. But they exacerbate dynamic power consumption thanks to increased pin capacitances.… Read More
For 5G to really deliver on its promise of high bandwidth and good coverage, it needs to use an RF band known as C-Band (3.7 to 4.4 GHz). This band is ideal because its frequency is high enough to offer 100MHz wide channels and also low enough that signal attenuation, especially in urban areas, is minimal. In 2020 the FCC auctioned off… Read More
Altair® Accelerator™ was the focus of a couple of SemiWiki posts last year. The most recent post covers the enterprise-grade job scheduler’s latest updates and an earlier one discussed its patented Rapid Scaling feature. You can refer to these blogs here. While these posts provide insight into how Accelerator can help increase… Read More
Over the past three years, I’ve spoken frequently with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to understand how the company is helping engineers cope with the challenges of chip design and verification. With their broad customer base and many years of experience in the EDA business, the folks at AMIQ really seem to … Read More
Last Thursday Intel held their investors meeting, in this write up I wanted to focus on my areas of coverage/expertise, process technology and manufacturing.
Technology Development presented by Ann Kelleher
Last year Intel presented their Intel Accelerated plan and, in this meeting, we got a review of where Intel stands on that… Read More
ON, ACLS, RMBS, AOSL, CAMT, ICHR, ONTO, SUMCO, and more!
SUMCO was the best call I read this quarter. There were many great bits of information but I want to start with the stat that really shocked me.
First of all, with regard to the LTAs out to 2026 and whether we did make progress in the last 3 months, that is correct. In the last 3 months,
-Production constraints push backlog up $1.3B to $8B
-Looks like $100B in WFE 2022 VS $80B in 2021
-Almost sold out for 2022- Could lead to continued growth 2023
-Insp/metrology up 68% Y/Y- Expect steady growth in 2022
Can’t keep up with demand….
Revenue came in at $6.27B and NonGAAP EPS of $1.89. A very slight beat of … Read More
Dan and Mike are joined by Matt Burns, technical marketing manager at Samtec. Matt focuses on why interconnect architecture has become so important for state-of-the-art system designs. The markets that are driving these requirements, along with the challenges and how to address them are provided.
The discussion concludes… Read More
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Intel’s Pearl Harbor Moment