More Headwinds - CHIPS Act Chop? - Chip Equip Re-Shore? Orders Canceled & Fab Delay- CHIPS Act more likely to be maimed…Read More
Next Generation of Systems Design at SiemensElectronic systems design is filled with a wide…Read More
Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI SummitAI is exploding everywhere. We’ve all seen the…Read More
Tier1 Eye on Expanding Role in Automotive AIThe unsettled realities of modern automotive markets (BEV/HEV,…Read More
A familiar face in EDA, Greg Lebsack met with me in the Empyrean booth at DAC this year on opening day to provide an update on what’s new. I first met Greg when he was at Tanner EDA, then Mentor and Siemens EDA, so he really knows our industry quite well. The company was a Silver level sponsor of DAC this year, and Empyrean offers tools for… Read More
The demand for high-performance and sustainable computing and networking silicon for AI has undoubtedly increased R&D dollars and the pace of innovation in semiconductor technology. With Moore’s Law slowing down at the chip level, there is a desire to pack as many chiplets as possible inside ASIC packages and get … Read More
PieceMakers, a fabless DRAM product company, is making waves in the AI industry with the introduction of a new DRAM family that promises to outperform traditional High Bandwidth Memory (HBM). The launch event featured industry experts, including a representative from Samsung, highlighting the significance of this innovation.… Read More
With all the Q2-24 results delivered, it is time to remove the clouds of euphoria and panic, ignore the performance claims and the bugs, and analyse the Data Center business, including examining the supply chain up and downstream. It is time to find out if the AI boom in semiconductors is still alive.
We begin the analysis with the … Read More
Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More
Yogish Kode is a senior solutions architect with substantial experience in product lifecycle management for over 20 years. His focus has been on semiconductor PLM and IP management. Prior to founding Glide Systems, he was a global solutions architect at Dassault Systèmes, an IT lead at Xilinx, and a senior programmer/analyst… Read More
This was my 40th Design Automation Conference and based on my follow-up conversations inside the semiconductor ecosystem it did not disappoint. The gauge I use for exhibitors is “qualified customer engagements” that may result in the sale of their products. This DAC was the best for that metric since the pandemic, absolutely.… Read More
At IEDM 2019, TSMC revealed two versions of 5nm standard cell layouts: a 5.5-track DUV-patterned version and a 6-track EUV-patterned version [1]. Although the metal pitches were not explicitly stated, later analyses of a 5nm product, namely, Apple’s A15 Bionic chip, revealed a cell height of 210 nm [2]. For the 6-track … Read More
Dan is joined by Dave Kelf, CEO of Breker Verification Systems, whose product portfolio solves challenges across the functional verification process for large, complex semiconductors. Dave has deep experience with semiconductor design and verification with management and executive level positions at Cadence, Synopsys,… Read More
Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More
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More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay