Traveling by car is something that I take for granted and I just expect that my trips will be safe, yet our cars are increasingly using dozens of ECUs, SoCs and millions of lines of software code that combined together present a target for hackers or system failures. The Automotive Safety Integrity Levels (ASIL) are known by the letters:… Read More




Siemens EDA on Managing Verification Complexity
Harry Foster is Chief Scientist in Verification at Siemens EDA and has held roles in the DAC Executive Committee over multiple years. He gave a lunchtime talk at DVCon on the verification complexity topic. He is an accomplished speaker and always has a lot of interesting data to share, especially his takeaways from the Wilson Research… Read More
Podcast EP153: Suk Lee’s Journey to Intel Foundry Services, with a Look to the Future
Dan is joined by Suk Lee, Vice President of Design Ecosystem Development at Intel Foundry Services. He has over 35 years of experience in the semiconductor industry, with engineering, marketing, and general management positions at LSI Logic, Cadence, TI, Magma Design Automation and TSMC. At TSMC, he was responsible for managing… Read More
Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization
Are you developing or thinking about developing your own RISC-V processor? You’re not alone. The use of the RISC-V ISA to develop processors for SoCs is a growing trend. RISC-V offers a lot of flexibility with the ability to customize or create ISA and microarchitectural extensions to differentiate your design no matter your application… Read More
Optimizing Return on Investment (ROI) of Emulator Resources
Modern day chips are increasingly complex with stringent quality requirements, very demanding performance requirement and very low power consumption requirement. Verification of these chips is very time consuming and accounts for approximately 70% of the simulation workload on EDA server farms. As software-based simulators… Read More
LIVE WEBINAR – The ROI of User Experience Design: Increase Sales and Minimize Costs
The semiconductor industry has seen a significant shift towards vertical integration of products, expanding from chips to generalized or purpose-built integrated solutions. As software becomes an increasingly critical component of these solutions, leveraging modern software development processes with User Experience… Read More
WEBINAR: Design Cost Reduction – How to track and predict server resources for complex chip design project?
During the design of complex chips, cost reduction is becoming a real challenge for small, medium and large companies. Resource management is a key to contain design cost.
The chip design market is expecting automated solutions to help in the resource prediction, planning and analysis. AI-based technologies are promising … Read More
Podcast EP152: An Informal Conversation with Aart de Geus on AI and Multi-Die at SNUG
This is a special edition of our podcast series. At the recent Synopsys SNUG User Group, SemiWiki staff writer Kalar Rajendiran got the opportunity to conduct an informal interview with Aart de Geus, Chairman and CEO of Synopsys.
What follows are some of Aart’s thoughts on the deployment of AI across the semiconductor … Read More
Multiphysics Analysis from Chip to System
Multiphysics simulation is the process of computational methods to model and analyze a system to understand its response to different physical interactions like heat transfer, electromagnetic fields, and mechanical structures. Using this technique, designers can generate physics-based models and analyze the behavior… Read More
Feeding the Growing Hunger for Bandwidth with High-Speed Ethernet
The increasing demands for massive amounts of data are driving high-performance computing (HPC) to advance the pace in the High-speed Ethernet world. This in turn, is increasing the levels of complexity when designing networking SoCs like switches, retimers, and pluggable modules. This growth is accelerating the need for … Read More
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