SILVACO 073125 Webinar 800x100

Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More


Podcast EP160: How Agile Analog Makes AMS Integration Easy with Chris Morrison

Podcast EP160: How Agile Analog Makes AMS Integration Easy with Chris Morrison
by Daniel Nenni on 05-05-2023 at 10:00 am

Dan is joined by Chris Morrison, Chris has 15 years’ experience in delivering innovative analog, digital, power management and audio solutions for International electronics companies, and developing strong relationships with key partners across the semiconductor industry. Currently he is the Director of Product Marketing… Read More


Chiplet Q&A with Henry Sheng of Synopsys

Chiplet Q&A with Henry Sheng of Synopsys
by Daniel Nenni on 05-05-2023 at 6:00 am

SNUG Panel

At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was the very personable Dr. Henry Sheng, Group Director of R&D in the EDA Group at Synopsys. Henry currently leads engineering for 3DIC, advanced technology and visualization.

Are we
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Memory Solutions for Modem, EdgeAI, Smart IoT and Wearables Applications

Memory Solutions for Modem, EdgeAI, Smart IoT and Wearables Applications
by Kalar Rajendiran on 05-04-2023 at 10:00 am

PSRAM Interface Controller Block Diagram

Memories have always played a critical role, both in pushing the envelope on the semiconductor process development front and supporting the varied requirements of different applications and use-cases. The list of the various types of memories in use today runs long. At a gross level, we can classify memories into volatile or … Read More


Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node… Read More


Using ML for Statistical Circuit Verification

Using ML for Statistical Circuit Verification
by Daniel Payne on 05-03-2023 at 10:00 am

6 sigma samples statistical circuit

I’ve been following Solido as a start-up EDA vendor since 2005, then they were acquired by Siemens in 2017. At the recent User2User event there was a presentation by Kwonchil Kang, of Samsung Electronics on the topic, ML-enabled Statistical Circuit Verification Methodology using Solido. For high reliability circuits… Read More


Gate Resistance in IC design flow

Gate Resistance in IC design flow
by Maxim Ershov on 05-03-2023 at 6:00 am

Figure1 9

MOSFET gate resistance is a very important parameter, determining many characteristics of MOSFETs and CMOS circuits, such as:

• Switching speed
• RC delay
• Fmax – maximum frequency of oscillations
• Gate (thermal) noise
• Series resistance and quality factor in MOS capacitors and varactors
• Switching speed and uniformity… Read More


Achieving Optimal PPA at Placement and Carrying it Through to Signoff

Achieving Optimal PPA at Placement and Carrying it Through to Signoff
by Kalar Rajendiran on 05-02-2023 at 10:00 am

PreRoute PostRoute Net Length Correlation

Performance, Power and Area (PPA) metrics are the driving force in the semiconductor market and impact all electronic products that are developed. PPA tradeoff decisions are not engineering decisions, but rather business decisions made by product companies as they decide to enter target end markets. As such, the sooner a company… Read More


Anirudh Keynote at Cadence Live

Anirudh Keynote at Cadence Live
by Bernard Murphy on 05-02-2023 at 6:00 am

IMG 0064

Anirudh is an engaging speaker with a passion for technology. Acknowledging the sign of the times, he sees significant value-add in AI but reminded us that it is a still supporting actor in system design and other applications where star roles will continue to be played by computational software that’s founded in hard science, … Read More


Formal-based RISC-V processor verification gets deeper than simulation

Formal-based RISC-V processor verification gets deeper than simulation
by Don Dingee on 05-01-2023 at 10:00 am

End to end formal-based RISC-V processor verification flow for the Codasip L31

The flexibility of RISC-V processor IP allows much freedom to meet specific requirements – but it also opens the potential for many bugs created during the design process. Advanced processor features are especially prone to errors, increasing the difficulty and time needed for thorough verification. Born out of necessity, … Read More