These days, the flows that are used to build semiconductor designs are rightly regarded as part of the intellectual property of the company that developed and used them.
But it didn’t always used to be that way.… Read More
Speculation: Silicon’s Most Expensive CompulsionHow Time-Based Scheduling Reclaims Silicon Wasted by Speculative…Read More
Exploring the Hidden Complexity of Modern Power Electronics Design – A Siemens White PaperReview the specifications of any state-of-the-art microcontroller and…Read More
Renesas Scalable Automotive SoC Design Using Arteris NoCThe increasing complexity of advanced driver assistance systems…Read MoreThese days, the flows that are used to build semiconductor designs are rightly regarded as part of the intellectual property of the company that developed and used them.
But it didn’t always used to be that way.… Read More
Keynote #2 at SNUG 2012 was John Cornish, VP Marketing at ARM. Why they sent a marketing person to speak in front of 2,000+ engineers I do not know. To top that, next time they should send a sales person and do a real dog and pony show. To find out more about John I checked his LinkedIn profile which was bare. So enough about John, lets hit … Read More
SNUG Chairman John Busco opened the session with a few words about Aart de Geus, the silver anniversary of Synopsys, and some SNUG statistics. A whopping 2,500 people registered this year! Probably due to the Magma acquisition which is prominently displayed on “Welcome Magma Users” signs and on the flat screens which are everywhere.… Read More
Before I get too snarky here, I would like to thank Synopsys for the invitation to SNUG 2012 and including me with the professional editors at a 75 minute roundtable discussion with Synopsys CEO Aart de Geus. While Aart is not my favorite big EDA CEO (Wally Rhines of Mentor bought me lunch and returns my email), he is definitely the most… Read More
And no red and green glasses required.
I remember the first time I heard about a Through Silicon Via (TSV), punching a hole through the entire wafer to make an electrical connection at the back, like we do all the time in printed circuit boards with through plated holes. I thought someone was trying one on and trying to make me look a fool.… Read More
Lip-Bu Tan, the CEO of Cadence, has been named by the Singapore Business Awards as Outstanding CEO (overseas) last week. These awards were launched in 1985 by the Business Times and DHL, so this year is the 27th year of the award, created to recognize business leaders in Singapore and abroad.
As it happens, Cadence flew me first class… Read More
Interesting article from Joel Hruska on ExtremeTech: Nvidia deeply unhappy with TSMC, claims 22nm essentially worthless . The title is a bit dramatic (poetic license) but the charts are accurate to the degree that 20nm costs will be significantly higher from the start and will continue to be higher throughout production and maturity.… Read More
The two large EDA companies offering SOC prototyping with FPGA-based boards are Synopsys and Cadence, however there’s a smaller vendor called Polaris Design Systems that also have a product in this important design verification category. I spoke on Wednesday with Rahm Shastry, CEO of Polaris to learn more about this company… Read More
Sometime early in 2013, Intel will tape out its first production chip for 14nm and it won’t be an x86 processor. It’s neither necessary nor prudent to lead with a new x86 processor when the one missing element that the mobile market desperately needs is nowhere to be found: an ultra low power 4G LTE chip that fits under the battery… Read More
The verification IP (VIP) for Non-Volatile Memory Express (NVMe) announcement from Synopsys is the first fruit issued from the acquisition of ExpertIO. With the proliferation of Nand Flash based storage equipment, or Solid State Drives (SSD), the move from pure SATA based solution was to be expected, sooner or later. Not because… Read More
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TSMC Technology Symposium 2026 Overview