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About the Job
Hands-on experience with employing constrained-random coverage driven verification methodology using UVM
Participating in deploying new methodologies to improve coverage and execution time in collaboration with other experienced engineers on the team
Working with the design team to validate and verify any requested design changes throughout the project life cycle.
Develop a thorough understanding of system-level design specifications. RTL Coding/Synthesis of the digital part of Mixed-Signal IPs. Develop behavioral models for the analog parts of Mixed-Signal IPs. Working with the verification team to develop advanced test plans. Working with the Mixed-Signal team on the co-simulation and verification of the IPs. Hardware verification of the digital module using cutting-edge FPGA kits.
Job Requirements
B.Sc. or M.Sc. in Electronics Engineering
5+ Years of experience in developing SV-based verification environments.
Strong knowledge of Verilog, System Verilog, and object-oriented
Computer skills required: Unix/Linux operating system
Strong knowledge of Verilog, System Verilog, and object-oriented programming languages
Knowledge of at least one standard verification methodology (such as VMM, OVM, or UVM)
Familiarity with RTL design, synthesis, and CDC analysis is a plus
Working knowledge of shell, Perl, and TCL scripting is a plus
Experience with clock domain crossing and reset architecture.
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