Designing for Ultra-Low Power? Easier with “CLICK” IP

Designing for ultra-low power will become the mantra for many of the new SoC designs, but the related SoC architecture can be very complex to handle. Make or buy is the project manager choice, but if you decide to ask for an expert advice before jumping start an ULP SoC design, attending thiswebinar from Dolphin Integration “The Proven Recipe for ULP SoC” may be wise.
I know Dolphin since 1987 when the company was designing the PIAF for the smart card inventor (Roland Moreno) as he wanted to re-invest the money flowing from the smart card patent rights into applications linked with the invention. The PIAF was a smart card reader system dedicated to car parking in France. The driver was buying a card and the reader, and just leave this reader inside his car when parking as a proof of payment. The major requirement of the system was to be… low power.

The mixed-signal chip was designed in 2 micron (2,000 nm), designing for low power was like a revolution at that time, as every chip maker was trying to offer the best performance, the higher chip frequency.

You now better understand why Dolphin Integration is sharing in 2016 their 30 years’ experience in low power design. Dolphin is proposing a complete methodology, including the various IP developed to support Ultra-Low Power design, the central activity controller, resource controller and local activity controller as shown in the picture below.

Chip designers are more and more involved in the design of connected devices, most often battery powered, and one of the main goals is to drastically decrease the chip power consumption. A few years ago, the race for high performance at reasonable cost was the main goal, except for the teams designing for wireless mobile applications. Many chip-makers have to adapt their design practices to the challenge of designing for low power, and even for ultra-low power.

When deciding to select the Dolphin’s solution, you are not only dealing with the make vs buy question. Designing a power aware SoC architecture significantly increase design complexity, impacting development schedule and cost, and could jeopardize the project if you miss the TTM window. Dolphin knows that dynamically switching the power domains on and off can lead to severe noise issues. Selecting a proven pre-defined embedded control network instead of designing it from scratch can dramatically increase the level of confidence in your SoC design noise immunity. It will help the design team to efficiently implement these new techniques while staying on line with time-to-market (TTM) requirements.

This webinar will propose a step by step method for the adoption of more complex SoC architectures based on multiple power domains, which also require embedding the whole power regulation network. Dolphin will explain the rigorous methodology based on the step-wise analysis of the 4 intertwined embedded SoC networks: functional, clock, power regulation and mode control. The approach may look theoretical, but is very practical as for each network you can associate a set of silicon IP solutions that the designer could implement.

For the functional part of the circuit, you will implement the power gating of any power island or domain by using CLICK (the power island kit). As well the DELTA library of voltage regulators and monitors will be used to build the power regulation network of the SoC. Dolphin will present that is called “SoC Fabric IP” and which is a set of IP (voltage regulators, clock generators, monitors,…) allowing to implement a pre-defined embedded control network. The designer could develop a monolithic and full custom Activity Control Unit (ACU) or Power Management Unit (PMU / PMU logic), but such an homemade control network is known to be complex to develop, tedious to validate and little amenable to architectural updates.

Designing for ultra-low power will become the mantra for many of the new SoC designs, but the related SoC architecture can be very complex to handle. If the design team has to develop a monolithic and full custom Activity Control Unit (ACU) or Power Management Unit, he will certainly make it eventually. But doing so is like re-inventing the wheel, with the risk of falling in traps impacting the design schedule, the development cost and the time-to-market. In the worst case, the design integrity can be impacted by poor noise immunity, leading to a redesign. Make or buy is the project manager choice, but if you decide to ask for an expert advice before jumping start an uLP SoC design, attending this webinar from Dolphin is certainly a good idea!

Dolphin will hold another live webinar on December13, 5:00 PM GMT (9 AM PST). This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven methodology.
To register, use thiswebinarlink

By Eric Esteve from IPNEST