Empowering AI, Hyperscale and Data Center Connectivity with PAM4 SerDes Technology

The rapid expansion of data-intensive applications, such as artificial intelligence (AI), high-performance computing (HPC), and 5G, necessitates connectivity solutions capable of handling massive amounts of data with high efficiency and reliability. The advent of 224G/112G Serializer/Deserializer (SerDes) technology, utilizing PAM4 (Pulse Amplitude Modulation 4-level) signaling, represents a significant leap in addressing these demands. Yang Zhang, a senior product line manager at Cadence’s Silicon Solutions Group, gave a talk at the ChipEstimate.com Booth at the recent Design Automation Conference (DAC) on this topic.

Importance of PAM4 High-Speed SerDes

Increased Data Throughput: PAM4 modulation effectively doubles the data rate compared to traditional NRZ (Non-Return-to-Zero) encoding by transmitting two bits per symbol instead of one. This capability is critical for hyperscale data centers and AI applications, which require rapid data transmission to manage vast data volumes efficiently.

Power Efficiency: By enabling higher data rates without proportionally increasing the signaling rate, PAM4 technology manages power consumption and heat dissipation more effectively. This efficiency is vital for maintaining operational costs and thermal management in large-scale data centers.

Scalability and Integration: PAM4 SerDes supports high interconnect density, crucial for scaling data center networks. Its integration into advanced packaging solutions, such as chiplets and co-packaged optics, further enhances performance and scalability by reducing latency and improving signal integrity.

Use Scenarios for High-Speed SerDes

High-speed SerDes technology is highly adaptable, catering to various reach requirements essential for modern connectivity solutions. For long-reach (LR) applications, SerDes is suitable for backplane copper cables, chip-to-chip, and backplane scenarios, ensuring reliable communication over extensive distances. Medium reach (MR) applications, such as chip-to-chip, benefit from a balance of performance and distance. Meanwhile, short reach (VSR and XSR) are ideal for chip-to-module, near-package optics, die-to-die and co-packaged optics applications, offering ultra-low latency and high bandwidth within a confined area.

These diverse application domains demonstrate the versatility and critical role of high-speed SerDes technology. In data centers, it supports the essential need for rapid and reliable data transmission within and between facilities. AI and HPC applications demand high bandwidth and low latency to efficiently process large datasets, a requirement well-served by SerDes technology. With the advent of 5G, telecommunications also benefit significantly from high-speed SerDes, ensuring robust and high-speed connections that facilitate seamless transfer of substantial amounts of data.

Ethernet in Data Center Operations

Ethernet technology is integral to data center operations, providing versatile solutions across long-reach, medium-reach, and short-reach applications. For long-reach, Ethernet connects various parts of the data center infrastructure over longer distances. Medium-reach Ethernet supports chip-to-chip scenarios, balancing performance and distance. Short-reach Ethernet caters to chip-to-module, near-package optics, die-to-die and co-packaged optics applications, ensuring ultra-low latency and high bandwidth within confined spaces. These varied applications underscore Ethernet’s critical role in maintaining efficient, high-performance data center operations.

The Ultra Ethernet Consortium (UEC)

While ethernet solutions are optimized for low latency to support high-speed data transfers and efficient processing, continued advancements are crucial. The Ultra Ethernet Consortium (UEC), founded under the Linux Foundation, aims to enhance Ethernet for high-performance computing and AI applications. UEC’s mission is to develop Ethernet-based solutions that rival technologies like InfiniBand, offering flexibility, high performance, and cost-effectiveness. By improving Ethernet’s transport layers and introducing features such as advanced congestion control and multi-pathing, UEC seeks to meet the specific needs of AI and HPC workloads.

Cadence’s Leadership in SerDes Technology

The company’s solution offerings include industry-leading 224G/112G/56G PHY IPs and controller IPs. These solutions not only support subsystems up to 800G/1.6T but also exhibit exceptional silicon performance, proven in both Cadence test chips and customer production chips.

In addition to LR, MR, VSR and XSR support, Cadence’s solutions support Ultra Long Reach (ULR) as well. Through its membership in the UEC, Cadence also plays an active role in the UEC’s effort to advance ethernet to support future AI and HPC applications demands.

Highlights

Maximum Likelihood Sequence Detector (MLSD) and Reflection Cancellation are two main features of their SerDes solutions.

The integration of MLSD in high-speed SerDes technology represents a significant advancement in signal processing for data transmission. By leveraging the Viterbi algorithm, MLSD provides substantial improvements in BER and mitigates the effects of far-out reflections, all while maintaining power efficiency. These are important, particularly in applications requiring low latency and high bandwidth, such as AI, HPC, and data center connectivity.

The incorporation of reflection cancellation techniques helps improve the Bit Error Rate (BER) and overall reliability of data transmission. Reflections can be caused by various design impairments such as connector coupling, package/PCB impedance mismatch, and package crosstalk, significantly impacting the link’s BER in production systems. Reflection cancellation can improve BER by one to two orders of magnitude.

Summary

The deployment of 224G/112G PAM4 SerDes technology is crucial for meeting the increasing demands of hyperscale connectivity, AI, and networking applications. Cadence’s advanced SerDes solutions, with their proven performance and versatility, play a significant role in this technological shift. As the industry continues to evolve, the innovations led by consortia like the UEC will further enhance Ethernet’s capabilities, ensuring it remains a cornerstone of global communication and data exchange infrastructure.

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