Webinar: Efficient Design Methodology for 112G Interface Compliance

Webinar: Efficient Design Methodology for 112G Interface Compliance
by Admin on 02-07-2024 at 11:13 pm

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance,… Read More


Webinar: Efficient Design Methodology for 112G Interface Compliance

Webinar: Efficient Design Methodology for 112G Interface Compliance
by Admin on 12-26-2023 at 8:30 pm

Description

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet… Read More


Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
by Kalar Rajendiran on 12-19-2023 at 6:00 am

Alphawave Semi 224G SerDes 1st TestChip

In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More


TSMC N3E is ready for designs, thanks to IP from Synopsys

TSMC N3E is ready for designs, thanks to IP from Synopsys
by Daniel Payne on 10-12-2023 at 10:00 am

synopsys ucie phy ip min

TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched.  Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More


Solving the EM Solver Problem

Solving the EM Solver Problem
by Tom Simon on 04-03-2019 at 7:00 am

The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More


Getting to 56G Takes The Right Stuff

Getting to 56G Takes The Right Stuff
by Tom Simon on 02-04-2019 at 12:00 pm

During the 1940s when aerospace engineers were attempting to break the sound barrier for the first time, they were confronting a slew of new technical issues that had never been dealt with before, and in some cases never seen before. In subsonic flight airflow was predictable and well understood. In crossing the sound barrier, … Read More


DAC 2019 Will Be Even More IP Friendly!

DAC 2019 Will Be Even More IP Friendly!
by Eric Esteve on 01-21-2019 at 12:00 pm

DAC 2019 will take place in Las Vegas (June 2-6) this year before moving back to San Francisco in 2020 and for the next 5 years. Considering the various rumors about merging the conference, or even the end of DAC, this is a very good news! Not only for Design Automation, but, as we will see, for the IP industry.

In fact, if we look at the exhibitor… Read More