TSMC to reduce EUV layers for 3nm as part of CIP

[IanD]

Sorry, Intel 4 is 13 layers. So it is 25 layers for N3 and 13 layers for Intel 4.

So Intel 4 is 2 EUV layers less (13) than TSMC N5 (15) but supposedly half-a-node denser?

I somehow doubt that TSMC use EUV layers where they're not needed, and I also doubt that Intel (with no real EUV experience) know better then TSMC (now on their 3rd EUV process *in mass production*) about how many EUV layers are needed to get a high-yielding process -- in fact, precisely the reverse, given Intel's track record.

I'll believe all those Intel 4 numbers when it's in volume production with yield as good as TSMC... ;-)

 

[Eric Bouche]

There has always been a large difference in lithography between tsmc foundry and Intel microprocessor. The number of EUV layers depends of the design rules.