TLA and process information tabs needed

[cliff]

The Intelians speak in code that is foreign to us outsiders. The three letter acronyms make me sad because I cannot follow along with these well thought out cryptic discussions. Furthermore, I have no idea what these process nodes offer. The process numbers have no meaning.

Dan, can you add a new menu tab called "Jargon" that allows users to choose "TLA definitions" or "Process features". Process features should probably include CPP choices (see, I am doing the TLA thing), the M2 pitch at the lowest voltage, the fin pitch, the lowest and highest single patterned 1x layer, the number of thicker layer (stack to the max).

Do schools near Portland offer Intelian language courses? They don't here in Arizona, not yet anyway. I heard TSMCish classes begin this fall.

 

[nghanayem]

I am a so sorry, TSMCish is not my'a first language.

 

[blueone]

Linus Torvalds has a few things to say about TLAs too, especially Intel's. In Torvalds' usual subtle style:

Linus Torvalds Bashes Intel's LAM - Rejected For Linux 6.2 - Phoronix

www.phoronix.com

 

[rjbrown747]

The Intelians speak in code that is foreign to us outsiders. The three letter acronyms make me sad because I cannot follow along with these well thought out cryptic discussions. Furthermore, I have no idea what these process nodes offer. The process numbers have no meaning.

Dan, can you add a new menu tab called "Jargon" that allows users to choose "TLA definitions" or "Process features". Process features should probably include CPP choices (see, I am doing the TLA thing), the M2 pitch at the lowest voltage, the fin pitch, the lowest and highest single patterned 1x layer, the number of thicker layer (stack to the max).

Do schools near Portland offer Intelian language courses? They don't here in Arizona, not yet anyway. I heard TSMCish classes begin this fall.

The Intelians speak in code that is foreign to us outsiders. The three letter acronyms make me sad because I cannot follow along with these well thought out cryptic discussions. Furthermore, I have no idea what these process nodes offer. The process numbers have no meaning.

Dan, can you add a new menu tab called "Jargon" that allows users to choose "TLA definitions" or "Process features". Process features should probably include CPP choices (see, I am doing the TLA thing), the M2 pitch at the lowest voltage, the fin pitch, the lowest and highest single patterned 1x layer, the number of thicker layer (stack to the max).

Do schools near Portland offer Intelian language courses? They don't here in Arizona, not yet anyway. I heard TSMCish classes begin this fall.

It's true that Intel code has existed for decades, and it is intentional to help manage IP. From a technology node perspective, the 1st numbers are generally wafer size. For example, 6xx, 8xx and 12xx. The last digits relate to the "Intel generation" and linked to technology node & nominal transistor width. For example, P648 could be 6" wafers @ 1.0um technology, P856 would be 0.25um on 8" wafers and P1266 is on 12" wafers at 45nm. Many Intelian's know their own technology introduction & inflection points (ex. intro to HKMG, 193i, EUV, FinFET, Ta/TaN liners, etc.) Anyway, the node digits progress as even numbers and align to the shrink. I invite you to check-out for some add'l public guidance: https://en.wikichip.org/wiki/intel/process. Good luck!