Technology has turned into a control freak!

[Ginger Grant]

I’ve known Technology for over 20 years. In the honeymoon period (those first 3years) Technology was very accommodating. The rules were very forgiving and I had the freedom to be creative. I’m a layout designer and a bit of an artsy person so this was extremely satisfying!

As time went on it was apparent Technology was pursuing it’s own interests.

Over the past 8 years or so Technology has become a control freak! I should have seen this coming when it didn’t want rotating anymore. I found that strange but it had excuses for this. Then it wanted dummy this and dummy that everywhere. Before I knew it even the dummy things had extreme rules! Now it is telling me exactly where to place things!

They say with all relationships it takes 2 sides working hard to make it work. That maybe true but Technology is simply becoming a control freak! My freedom for creativity is nearly squashed! What was an art form is now serious and frustrating work! What can a person do to take some control back!

<script src="//platform.linkedin.com/in.js" type="text/javascript"></script>
<script type="IN/Share" data-counter="right"></script>

 

[Ginger Grant]

In all seriousness I'm referring to the deep sub micron process technology nodes. They have become so complex that layout must devise ways to avoid all the 'customization' techniques which was so easily done in the past. Some of the newer tools help with this process but it has become apparent that we really need to push both technology and tools far more to ease the 'layout' requirements that these process nodes demand. Any suggestions or observations that can be shared would be much appreciated!

 

[Daniel Payne]

Ginger,

Yes, with Restricted Design Rules the days of artistic freedom in IC layout have come to an end.

Even back in 1982 when the first double level metal process was being designed at Intel we were asked by the process development engineers if we could live with Metal 1 oriented vertically and Metal 2 always oriented horizontally. We told them, "No way, Jose". Today it's a different story because we need RDR to produced chips that yield at 20nm and smaller nodes.

 

[Ginger Grant]

Daniel, M1 and M2 in opposite directions considered an unreasonable requirement? Too funny!

When we embarked on 28nm 3 years or so back we were whining how much trouble that process put us through. Now I have a great appreciation for 28nm. 20nm was a huge adjustment and continues to be and before we really became comfortable with that we are now tackling the finfet process.

I think in reflection that we really have to let go of the way we design and layout circuits for these new processes. Design and layout techniques of 28 and above simply do not conform to the new constraints and requirements of these latest process nodes.

 

[Randy Smith]

The basis of the problem is that the lithography equipment vendors never improved on the equipment. It is though the chips are being drawn with large crayon when you want the resolution of a sharp needle. In order to get he chips to work at all you have to eliminate patterns that do not print well, keep the lines at specific pitches, and place ever increasing restrictions to keep yield acceptable. In order for this to improve you need a better way to create the chip - better light source or a new method other than photo lithography.

 

[Ginger Grant]

In order for this to improve you need a better way to create the chip - better light source or a new method other than photo lithography.

I agree, but I think it needs to go even further in that layout now needs to be a set pattern which design would need to conform to. These process nodes require restrictive routing rules and predictable patterns to improve yield. Therefore, design engineers need to consider this and design for these constraints.

 

[Staf_Verhaegen]

The basis of the problem is that the lithography equipment vendors never improved on the equipment. It is though the chips are being drawn with large crayon when you want the resolution of a sharp needle. In order to get he chips to work at all you have to eliminate patterns that do not print well, keep the lines at specific pitches, and place ever increasing restrictions to keep yield acceptable. In order for this to improve you need a better way to create the chip - better light source or a new method other than photo lithography.

I object this statement. The lithography equipment is I think the most complicated and engineering advanced equipment used in the whole semiconductor production cycle. It's just that we are reaching the limits of physics. A lot of alternatives have been tried (X-Ray, imprint, electron projection, ...) but never succeeded.

 

[LinkedIn]

Oscar Law • Those RDR rules are based on the process limitation but not the circuit design guideline. I really want to see more design guideline for matching, transistor placement, shielding recommendation.

 

[Randy Smith]

Do you really think they could not have created something a a smaller wavelength, or was it just that it was not a good financial bet with the shrinking number of fabs at each node? Physics does allow for wavelengths below 193nm.

 

[Daniel Payne]

Randy san,

With a smaller wavelength of light the depth of field also gets smaller, enough that you start to loose focus and slow down the throughput.

 

[Randy Smith]

Oscar Law • Those RDR rules are based on the process limitation but not the circuit design guideline. I really want to see more design guideline for matching, transistor placement, shielding recommendation.

I do not get your point. These are process design rules. The role of the foundry is to tell you what process rules to follow so as to get reasonable yield. This next layer of rules depends on layout IP that may come from the foundry or from some other IP provider. Your request is reasonable, but it will not necssarily come as a standard foundry service. This information can be derived from the DRM along with other information that the foundries provide. You need tools and considerable expertise - but companies doing the designs on the bleeding edge are making it happen

 

[Randy Smith]

Randy san,

With a smaller wavelength of light the depth of field also gets smaller, enough that you start to loose focus and slow down the throughput.

Daniel, yes you are correct, but we have seen advances such as immersion lithography and polarized light sources come into play since the current light wavelength was adopted. Is it not reasonable to think that smaller frequencies could be utilized given some of these more recent advancements?

 

[Ginger Grant]

It is just a matter of time before it is molecular.. and once they control the molecules there will be no need for silicon anymore.. we can build circuits on practially anything.. including our own skin! .. ok.. I know.. totally sci fi .. or is it?

 

[Staf_Verhaegen]

Physics does allow for wavelengths below 193nm.

I fact they tried 157nm but it failed and 193nm immersion saved the day (wavelength of 193nm light in water is actually smaller than 157nm). Problem with smaller and smaller wavelengths is that more materials will block the light. For 157nm the optical path had to be nitrogen purged because normal air absorbs too much 157nm light. EUV will be done in near vacuum.

greets,
Staf.

 

[LinkedIn]

Stefan Zollner • I have a very simple suggestion for you: Why don't you draw lines no smaller than one micron. Your designs will be much more expensive and run much more slowly, but you will have all the artsy freedom your spirit requires. If you insist on printing features much smaller than an optical wavelength, then, unfortunately, certain rules need to be followed to allow the lines to print and have the margins for processing. As a process engineer, I always found it interesting how different layouts will influence the structures we built. Regards Stefan

 

[Ginger Grant]

Stefan Zollner • I have a very simple suggestion for you: Why don't you draw lines no smaller than one micron. Your designs will be much more expensive and run much more slowly, but you will have all the artsy freedom your spirit requires. If you insist on printing features much smaller than an optical wavelength, then, unfortunately, certain rules need to be followed to allow the lines to print and have the margins for processing. As a process engineer, I always found it interesting how different layouts will influence the structures we built. Regards Stefan

Layout designers translate circuit designs to layout so we do not have freedom to draw the line sizes of our choice. It is all dictated in the circuit.

If you really think about it (and we try not to think about it all the time) we are constrained under a plethora of rules. Process Rules, Circuit Rules, Restrictive Design Rules, Design for Manufacturing rules, design constraints, and even our own tools have rules (example: VXL compliant), .. the list goes on.

I'm beginning to think that the only way one can be a good layout designer is to be extremely submissive!

 

[LinkedIn]

David Fried • A very interesting thread... Physics certainly does "allow for" wavelengths below 193nm, but all the other boundary conditions on building high-volume manufacturing lithography tools have basically stalled us at 193nm for a very very long time (like, since 90nm technology!). Tooling improvements (including immersion) have increased the Numerical Aperture, and therefore the 1D resolution (if you only wanted to print gratings). But, we've marched through about 5 technology nodes of dimensional scaling with the same fundamental patterning wavelength. This is what's forcing layout rules to be so restrictive. This really won't change until EUV makes its long awaited debut. The big question in my mind is this: When EUV comes online (finally!), will the designers get many or all of their freedoms back? This question is part patterning physics and part Technology-Design culture!

 

[MattDunn]

Stefan Zollner • I have a very simple suggestion for you: Why don't you draw lines no smaller than one micron. Your designs will be much more expensive and run much more slowly, but you will have all the artsy freedom your spirit requires. If you insist on printing features much smaller than an optical wavelength, then, unfortunately, certain rules need to be followed to allow the lines to print and have the margins for processing. As a process engineer, I always found it interesting how different layouts will influence the structures we built. Regards Stefan

Stefan, layout designers are most often in business of optimizing layout in terms of area, performance, and DFM, taking advantage of all process features that new nodes have to offer. Sadly, mask designers can't simply design to satisfy their artistic spirit. Furthermore, in many of the very advanced nodes, your suggestion would not work:

As Ginger is stating, very advanced processes are becoming so restrictive, that many design rules are fixed at specific values or may be restricted to a very narrow range of values. Just 'drawing things big' is simply not allowed in these processes, at least not in the layers where most layout designers enjoy their artistic freedom the most: the base layers. (Mind you, drawing shapes larger than optical wavelength even in metals is becoming disallowed as well.)

Ginger, I sympathize with your perspective as a mask designer. Indeed with all these rules, it seems all artistic freedom that we once enjoyed is stifled. However, I believe there is still room for artistic expression in mask design, in one of two ways:
1. at a polygon level, design rules are so restrictive that I agree it seems that simply being compliant makes for a good layout designer. However, IMO, there is still enough flexibility to be found in the design rules to exercise artistic license. The hard part is finding that flexibility, amidst a 'maze' of design rules. It will typically require a mask designer of significant familiarity in the given process to understand all of the design rules (and all at once, to boot) to experty find this flexibility. Alas, whether this is considered artistry, or simply problem solving is arguable.
2. at a higher hierarchical level, there are many clever ways to apply artistic license with the assembly of 'groups of objects'. Designing cell boundary interfaces that can be used in more analog layouts (rather than being similar to standard cells), I would consider an art. Employing more of these macro level rules (often additional self-imposed) will facilitate much more layout reuse (hence avoiding sometimes painful polygon level layout), and the repeatability and consistent nature of the layout would make it all the more DFM friendly. Rather than 'layout design', perhaps a more apt description of this would 'layout hierarchy design'? I think there is art to be found here.

Matt

 

[Ginger Grant]

1. at a polygon level, design rules are so restrictive that I agree it seems that simply being compliant makes for a good layout designer. However, IMO, there is still enough flexibility to be found in the design rules to exercise artistic license. The hard part is finding that flexibility, amidst a 'maze' of design rules. It will typically require a mask designer of significant familiarity in the given process to understand all of the design rules (and all at once, to boot) to experty find this flexibility. Alas, whether this is considered artistry, or simply problem solving is arguable.

Matt

Thanks Matt. Layout designers must possess strong right and left brains to plug away at their responsibilies. The honest truth is that layout design is an art no matter how many restrictions and rules apply.

In today's newest technologies designing for yield and manufacturablility is receiving a lot of attention! Layout Dependent Effects (LDE) such as Well Proximity, Poly and OD spacings, geometric layer sizes, Diffusion lengths and so on all play a part on stress, dopants, lithography and so on. I believe Cadence has been spending time addressing these issues with some of it's tools in Version 12! I'm not talking ISR either.. I'm talking about their jump to V12. The burden for layout that is DFM and DFY is on both the design engineer and layout with a huge emphasis on preventing cost on the iteratives loops to optimize the design for performance!

What can I say, I love this job!