Single fin device DTCO

[nghanayem]

For many years now further density improvements have been off of the back of fin depopulation. Ordinarily this would come at a large performance cost, but with new nodes better transistors offset this performance degradation with better transistors that are slightly stronger in spite of the lower fin counts. On the Samsung 7nm family a single fin UHD library was created, with finflex single fin devices are mixed with dual fin devices, and it seems like there might well be a pure single fin library for the N3 family in the works. In all of these instances the pure single fin libraries seem to offer too little performance to be practical and theoretical densities cannot be realized due to metal pitch limitations.

Another scaling opportunity that has hit practical limits is fin height. Taller thinner fins give better channel control and greater drive, but are less sturdy and increases capacitance between the other fins. If we were just to look at the front end, can both of these scaling limiters be used to "fix" each other? In theory if someone wanted to make a more compelling single fin device, could they abuse the fact that fin pitch is so much larger to make extra tall fins to get around the single fin device drive issues without driving parasitic capacitance through the roof? In practice this wouldn't be super successful due to the metal pitch scaling issues, and HNS having similar std cell size with greater performance and leakage. However I did think it interesting, and it would probably make any N3 single fin nodelet more compelling than the alternative of just being the same fin as regular N3E.

 

[Tanj]

I've read that the N3 single fin and maybe 1-2 libraries are intended to be mixed on the same chip with other logic. Consider alternating a 1-1 row between 2-2 rows, allowing perhaps some slow paths to be implemented with low power. It seems clear that you are unlikely to have whole chips done in the more extreme library. That would imply that fin height stays the same everywhere. It also might mean that 1-1 rows can borrow some routing space over neighbors and maybe also tolerate some dark silicon in order to get some kind of overall optimization of power, with the EDA trained to judge when it could be useful to throw in the other kinds of row.

 

[nghanayem]

I've read that the N3 single fin and maybe 1-2 libraries are intended to be mixed on the same chip with other logic. Consider alternating a 1-1 row between 2-2 rows, allowing perhaps some slow paths to be implemented with low power. It seems clear that you are unlikely to have whole chips done in the more extreme library. That would imply that fin height stays the same everywhere. It also might mean that 1-1 rows can borrow some routing space over neighbors and maybe also tolerate some dark silicon in order to get some kind of overall optimization of power, with the EDA trained to judge when it could be useful to throw in the other kinds of row.

Yeah finflex is one thing and the mixed 2/1 fin will probably have it's use cases. But N3S I am more skeptical on. I don't think they can really shrink pitches at all given the cost and throughput issues of N3, so to me that indicates that N3S might just be the 1 fin N3E from finflex as a full library. If that is the case then I think it will be like the 5LPE UHD library. Great for headlines, effectively useless in practice. Hence why I was theorizing that if you knew that your node would only be single fin, if you could rearchitect the transistor in such a way to maximize performance from a single fin device (kind of like how today double fins can give you excellent performance). Another side effect of this 1 fin only node is that your HP and HD libraries kind of merge into one.

 

[semiman]

That'll require more R&D expenditure. If TSMC tries to provide 'super' single fin device in 3nm node, then it'll not be 3nm anymore. You need to implement new contacts suited for that 'new' fins, dummy fin distance changes...etc it'll come at a price.