Semiconductor process node density, transistors, and how they create standard cells.

[goldstone77]

I'm trying to build up my knowledge with semiconductors with a focus how density, and nodes are being developed. Most of this comes from a YouTube presentation by Synopsys knowledge on the subject of the semiconductor process node, transistors, and how they create standard cells that influence microprocessor density. We know as we shrink the process down typical density advantage or disadvantages are going to disappear, and design will ultimately determine performance. Let's take a look at where we were, and where we are now. Please feel free to comment and help increase my understanding of the processes involved.




The short dimension is the length and the long dimension is the width. Click here for YouTube Link

This shows how node and matches up with gate pitch, and how it's relevant to density.

This list the advantages as well as some dimensions of a FenFET transistor. Note the Fin Width is also the effective length previously discussed. P fin is Fin pitch, which we will discuss later, and is very important for figuring out density.

One big thing to note here is that electrostatics take on a big roll in performance with FinFET transistors.

It's important to note that length to width ratio of ~2.5 needs to be maintained to help mitigate against short channel effects.

As the transistor has evolved it has increased in height while maintaining the L/W ratio ~2.5.

Now we get down to the nitty-gritty of what makes up a large portion of density. The dimensions of the standard cell library. Here we see Fin pitch(FP) determines how close, or far apart each Fin is to each other. Gate pitch(CGP) also called CPP(Contacted Poly Pitch) determines how close, or far apart each gate is. Multiply FP X CGP and you get the area of the transistor. IF you Multiply CGP X MP it gives you the Cell area.

Fin Depopulation reduces the size of the standard cell, which will increase density. Using the above coordinates for MP, CGP will show you where technology is in terms of node density.

Metal Track Scaling further reduces density by increasing area scaling, reduces power, but offers no performance gain. When scaling cell size by reducing tracks you have to depopulate the Fins, because they will not fit. This requires process adjustments like taller fins to maintain performance in a process called Design Technology Co-optimizations(DTCO). All other things being equal going from 3 fins to 2 fins would give you 2/3 the drive current unless the fins are taller. Maintaining performance while going to fewer tracks is the key area of focus right now. At some point we will be looking at one fin per cell.

This shows the transistor performance Node to Node with 9 track Cells, and without manipulation of electrostatics.

Electrostatics can improve transistor performance by 20%.

Microprocessor performance is evolving through Fin depopulation of the Standard Cell.

Reference:

[video=youtube;MLUSuw_MkMk]https://www.youtube.com/watch?v=MLUSuw_MkMk&ab_channel=Synopsys[/video]
[h=1]Designing 7-nm IP, Bring It On Moore![/h]<ytd-video-owner-renderer><yt-formatted-string id="owner-name">Synopsys</yt-formatted-string><ytd-badge-supported-renderer></ytd-badge-supported-renderer>
Published on May 3, 2016

</ytd-video-owner-renderer><ytd-expander collapsed-height="60"><yt-formatted-string id="description" split-lines="">In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA requirements. See how quantum effects impact FinFET designs in terms of fin width, fin height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance and power improvements.</yt-formatted-string>
</ytd-expander>