Latest update on EUV, immersion and ASML's roadmap for 2020-2025

[user nl]

On the ASML website you can find the latest details on ASML's EUV, immersion and holistic lithography roadmaps for 2020-2025. Furthermore, their estimate on revenue and EPS growth. Various detailed presentations from their top management on these topics and the semiconductor industry growth in general were discussed during their 2016 investor day in New York.

Enjoy the reading here:
ASML: General - MISC - Investor Day

User nl

 

[lefty]

I found an interesting article about EUV here:
Leading Chipmakers Eye EUV Lithography to Save Moore’s Law - IEEE Spectrum

The list price of ASML’s newest EUV machine exceeds €100 million, more than twice that of an average 193-nm scanner, says spokesperson Niclas Mika. It is about the height and width of a New York City bus and is shipped in multiple 747s. Customer estimates suggest such a machine, run at mass-production levels, could consume some 1.5 megawatts or so of electricity, significantly more than a 193-nm machine.

 

[Staf_Verhaegen]

Customer estimates suggest such a machine, run at mass-production levels, could consume some 1.5 megawatts or so of electricity, significantly more than a 193-nm machine.

Maybe one possible side fact to know is that EUV light is made by burning falling Sn droplets. This is done by (trying to) focus a laser on it. The spotsize of this laser has to be bigger than the droplet meaning that a lot of energy has to be absorbed at the back of the machine. My memory me be fooling me here now but I think I was once told that with the water cooling of this back side of the machine an EUV using fab could heat an office building near it.
From the light that then eventually leaves the EUV source only a few percent reaches the wafer the rest is absorbed in the mirrors of the lens.

 

[user nl]

No pain no gain...ASML invests 1 BEuro in ZEISS for high NA EUV

In the past ASML used the 'no pain no gain' mantra to have INTEL, TSMC and SAMSUNG pay for R&D by ASML in EUV via a 5 year co-investor program.

Now ASML moves to the other side of such deals investing 1 B Euro in lens supplier Zeiss SMT to develop the next generation high NA EUV scanners for 2020 and beyond:
ASML: Press - Press ReleasesZEISS and ASML Strengthen Partnership for Next Generation of EUV Lithography Due in Early 2020s - Press ReleasesZEISS and ASML Strengthen Partnership for Next Generation of EUV Lithography Due in Early 2020s

Happy to see a company investing their excess cash in R&D for future developments instead of buying back their own shares....

User nl

 

[lefty]

Does anyone think that EUV could be used in older nodes, like 14nm or 10nm once it becomes more mature (around 2020)? Considering that 14nm uses double patterning, would single patterning EUV save costs on that node?
I notice the Wikipedia entry says that SMIC will use EUV for their 14nm node (don't know if that's true or not)

 

[Fred Chen]

Does anyone think that EUV could be used in older nodes, like 14nm or 10nm once it becomes more mature (around 2020)? Considering that 14nm uses double patterning, would single patterning EUV save costs on that node?
I notice the Wikipedia entry says that SMIC will use EUV for their 14nm node (don't know if that's true or not)

An existent 10/14nm node line already shipping to customers would not be disrupted, but with SMIC currently setting up for 14 nm by 2020, they may consider waiting for EUV, but it's their gamble. Their supporting partner Qualcomm probably won't be able to wait that long.

14nm has one double patterning M1 layer, it may not be worth it, considering the whole process cost.

10nm has a double or triple patterning M1 layer, and a few other layers would become double patterning. But Samsung is already shipping 10nm Snapdragon to Qualcomm, or trying to. EUV complication is the last thing it needs.

 

[lefty]

Thanks for the answer.
So, it sounds like 10nm would be a good canditate for EUV. (Note, I'm talking about many years in the future, when all the clinks have been knocked out and EUV is more affordable)

 

[Fred Chen]

Thanks for the answer.
So, it sounds like 10nm would be a good canditate for EUV. (Note, I'm talking about many years in the future, when all the clinks have been knocked out and EUV is more affordable)

Only Samsung is really doing 10nm (others are skipping practically), they very likely wished to have EUV now but have to do it right now with good 10nm yields with multipatterning.

By 2020, there could be more options such as high NA EUV or SAQP, those might be applied to 5nm or a delayed 7nm. The 10nm SADP costs would probably be lower by then as well, e.g., cuts reduced or simplified, EUV costs would have to drop much lower to catch up. If the 10nm process has already been working well for so long, it would not be tinkered with, generally.

Waiting for EUV requires surviving without EUV. It demonstrates why any next-generation technology should not wait too long to be used.

 

[benb]

On the ASML website you can find the latest details on ASML's EUV, immersion and holistic lithography roadmaps for 2020-2025. Furthermore, their estimate on revenue and EPS growth. Various detailed presentations from their top management on these topics and the semiconductor industry growth in general were discussed during their 2016 investor day in New York.

Enjoy the reading here:
ASML: General - MISC - Investor Day

User nl

There are 8 PDFs, maybe not everyone on the board can read through all of these...So I'll summarize what I found interesting.
Martin Van Den Brink slides:
- Slides 3-7: Industrial revolution was the original Moore's law, and is going strong for 116 years without a hitch. Reassuring.
- Slide 10: Carbon nanotube TEM image. Pretty cool.
- Slide 13: How multi-patterning (LE) works. Very clear graphical summary.
- Slide 16: Graphic with grey "EUV" surrounding 2018 in logic.
- Slide 20: Support for the 2018 date: Samsung, Intel and TSMC quotes.
Hans Meiling slides:
- Slide 3: How much simpler EUV is compared to alternatives. Processes compared: LE3, LE4, ArFi Spacer Grating with 2 cuts, EUV single exposure.
- Slide 6: 7nm comparison: 54 ArFi vs. 9 EUV + 19 ArFi steps; EUV reduces wafer cost 12%.
- Slide 7: EUV also improves yield 9% and time to market by 6 months.
- Slide 8: EUV up to 1500 wpd in Sept 2016. 15 EUV orders Oct 2016.
- Slide 25: More comments by Intel, Samsung, TSMC and Global Foundries indicating 2018 to 2019 EUV insertion point.
- Slide 28: Estimates for demand for EUV systems in each segment, per fab. Logic 7-12.

 

[Fred Chen]

There are 8 PDFs, maybe not everyone on the board can read through all of these...So I'll summarize what I found interesting.
Martin Van Den Brink slides:
- Slides 3-7: Industrial revolution was the original Moore's law, and is going strong for 116 years without a hitch. Reassuring.
- Slide 10: Carbon nanotube TEM image. Pretty cool.
- Slide 13: How multi-patterning (LE) works. Very clear graphical summary.
- Slide 16: Graphic with grey "EUV" surrounding 2018 in logic.
- Slide 20: Support for the 2018 date: Samsung, Intel and TSMC quotes.
Hans Meiling slides:
- Slide 3: How much simpler EUV is compared to alternatives. Processes compared: LE3, LE4, ArFi Spacer Grating with 2 cuts, EUV single exposure.
- Slide 6: 7nm comparison: 54 ArFi vs. 9 EUV + 19 ArFi steps; EUV reduces wafer cost 12%.
- Slide 7: EUV also improves yield 9% and time to market by 6 months.
- Slide 8: EUV up to 1500 wpd in Sept 2016. 15 EUV orders Oct 2016.
- Slide 25: More comments by Intel, Samsung, TSMC and Global Foundries indicating 2018 to 2019 EUV insertion point.
- Slide 28: Estimates for demand for EUV systems in each segment, per fab. Logic 7-12.

Thanks for the reminder. I did download the presentations. Their process step counts/projections are indeed off but it makes a better story for the EUV development.

The notable ones are:
1) D1Y uses PD not PQ?
2) D1X (18 nm) should already be PQ
3) D20 SE? Should be LE2 or PD.
4) Logic cuts/vias at 10nm would not be LE3 but LE (LE2 in worst case, not optimized)
5) Logic cuts/vias at 14-16nm would be LE
6) Overlay tree for 10nm has too many branches, should be at most two in one row, maybe three for triple patterned M1.
7) Overlay tree for 7nm immersion seems to assume LE5 or SAQP+LE4, which are really the worst-case options. It also depends on the minimum pitch. SAQP+LE2 would probably be sufficient when the cuts are redistributed. Recent silicon etch shrink results by TEL and others* suggest might go down to SAQP+LE, can be pushed down to 44 nm cut pitch.
8) Overlay tree for 7nm EUV had some double patterning, which could happen for LE2 on some layers with end-to-end gap sensitivity. This scenario probably targeted a 32 nm pitch. Probably for this reason, recent 7nm EUV demonstrations have targeted a more relaxed 36 nm pitch.

It can be said that 193 nm immersion requires more patterning steps at earlier nodes than EUV, but the gap to EUV is effectively two generations which have already past the insertion point. That is, at 7nm, the patterning complexities are comparable though different.

*R. Nakayama, H. Ishii, K. Mikami, K. Tsujita, H. Yaegashi, K. Oyama, M. C. Smayling, V. Axelrad, "Pitch-based pattern splitting for 1D layout", Proc. SPIE vol. 9658, 96580A, from Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII. Effectively a deliberate sidelobe enhancement technique in negative-tone resist.